Patents Examined by Emmanuel Baynard
  • Patent number: 7010071
    Abstract: Method for forming and/or determining a synchronization sequence, a synchronization method, a transmitting unit and a receiving unit, the formation of synchronization sequences, which are based on partial signal sequences, includes a second partial signal sequence being repeated and modulated in the process by a first partial signal sequence.
    Type: Grant
    Filed: February 16, 2000
    Date of Patent: March 7, 2006
    Assignee: Siemens Aktiengesellschaft
    Inventors: Juergen Michel, Bernhard Raaf
  • Patent number: 6704378
    Abstract: An adaptive notch filter (ANF) module selectively filters a received wideband communication signal to eliminate narrowband interference that lies within the frequency spectrum of the wideband communication signal. To determine the presence of narrowband interference, the ANF module scans various known narrowband channels that lie within the frequency spectrum of the wideband communication signal and determines signal strengths for each of the narrowband channels. The signal strengths from the narrowband channels are compared to a threshold that is derived from the narrowband signal strengths. Narrowband channels having signal strengths that are greater than the threshold are determined to have interference.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: March 9, 2004
    Assignee: ISCO International, Inc.
    Inventors: Charles E. Jagger, Mark N. Willetts, Micolino Tobia
  • Patent number: 6219387
    Abstract: A metric circuit (53) and method for use in a viterbi detector (54) are provided. The metric circuit (53) provides a transition signal (56) to a trellis block (55) during a first period and a second period. The transition signal (56) includes a negative transition signal and a positive transition signal. The metric circuit (53) includes a first adder circuit (70), a second adder circuit (72), a first comparator (74), a second comparator (76), an odd sample/hold circuit (80), and an even sample/hold circuit (82). The metric circuit (53) receives a discrete signal and a threshold value at the first adder circuit (70) and the second adder circuit (72). The first is adder circuit (70) generates a first sum and the second adder circuit (72) generates a second sum.
    Type: Grant
    Filed: March 18, 1997
    Date of Patent: April 17, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Kerry C. Glover