Abstract: A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine.

Abstract: According to some embodiments, a system provides a resource service module, a resource data record repository, and a provider module. The resource service module exposes an interface, receives an invocation of the interface from a system management module, and requests managed resource data associated with a manageable resource based on the invocation. The resource data record repository includes a resource data record indicating a memory location of a managed host in which the managed resource data is stored, and the provider module receives the request and retrieves the managed resource data from the memory location of the managed host.

Abstract: A method for balancing the load of a parallel processing system having a plurality of parallel processing elements arranged in a loop, each processing element (PEr) having a local number of tasks associated therewith, wherein r represents the number for a selected processing element and each of the processing elements is operable to communicate with a clockwise and an anti-clockwise adjacent processing element, the method comprises determining a total number of tasks present within the loop, calculating a local mean number of tasks for each processing element, calculating a local deviation for each processing element, determining a running partial deviation sum for each processing element, determining a clockwise transfer parameter and an anti-clockwise transfer parameter for each processing element, and redistributing tasks among the processing elements in response to the clockwise transfer parameter and the anti-clockwise parameter for each of the processing elements.

Abstract: A data processing system is arranged to execute multiple program threads, with each program thread comprising program thread instructions. An interpreter is operable, during execution of each program thread, to employ a table pointer to reference a table to determine for a current program thread instruction a sequence of native instructions to be executed by the processor core to effect execution of that current program thread instruction. A consistency module is provided which is responsive to occurrence of a predetermined event to cause the table pointer to be manipulated, such that for a predetermined number of the program threads, the interpreter will be operable to associate a subsequent program thread instruction with a predetermined routine to be executed by the processor core, the predetermined routine being operable to cause the state of the corresponding program thread to be made available for subsequent reference.