Patents Examined by Eric Coleman
  • Patent number: 11029955
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • Patent number: 11029951
    Abstract: Examples of the present disclosure provide apparatuses and methods for smallest value element or largest value element determination in memory. An example method comprises: storing an elements vector comprising a plurality of elements in a group of memory cells coupled to an access line of an array; performing, using sensing circuitry coupled to the array, a logical operation using a first vector and a second vector as inputs, with a result of the logical operation being stored in the array as a result vector; updating the result vector responsive to performing a plurality of subsequent logical operations using the sensing circuitry; and providing an indication of which of the plurality of elements have one of a smallest value and a largest value.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Sanjay Tiwari
  • Patent number: 11029961
    Abstract: Various embodiments are described herein that relate to computer programs and computer-implemented techniques for predicting when jobs in the queue of a batch scheduler will be completed. More specifically, various embodiments are described herein that relate to mechanisms for predicting the wait time and/or the estimated time to completion for jobs that are to be executed by a software asset management platform. For example, heuristics and algorithms could be used to discover when execution of a job is likely to begin and/or end. The estimated time to completion for a given job can be estimated by summing the expected execution time of the given job and the expected execution times of any jobs to be executed prior to the given job, while the wait time for a given job can be estimated by summing the expected execution times of any jobs to be executed prior to the given job.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: June 8, 2021
    Assignee: Flexera Software LLC
    Inventor: Rajeesh Chirayath Kuttan
  • Patent number: 11029958
    Abstract: Systems, methods, and apparatuses relating to configurable operand size operation circuitry in an operation configurable spatial accelerator are described.
    Type: Grant
    Filed: December 28, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Chuanjun Zhang, Kermin E. Chofleming
  • Patent number: 11029953
    Abstract: Disclosed embodiments relate to the usage of a branch prediction unit in service of performance sensitive microcode flows. In one example, a processor includes a branch prediction unit (BPU) and a pipeline including a fetch stage to fetch an instruction specifying an opcode, an operand, and a loop condition based on the operand, wherein the BPU is to generate a hint reflecting a predicted result of the loop condition, a decode stage to generate either a first or a second micro-operation flow as per the hint, the pipeline to begin executing the generated micro-operation flow; a read stage to read the operand and resolve the loop condition; and execution circuitry to continue the generated micro-operation flow if the prediction was correct, and, otherwise, to flush the pipeline, update the prediction, and switch from the generated micro-operation flow to the other of the first and second micro-operation flows.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Michael Mishaeli, Ido Ouziel, Jared Warner Stark, IV
  • Patent number: 11023413
    Abstract: A method of operating a system comprising multiple processor tiles divided into a plurality of domains wherein within each domain the tiles are connected to one another via a respective instance of a time-deterministic interconnect and between domains the tiles are connected to one another via a non-time-deterministic interconnect. The method comprises: performing a compute stage, then performing a respective internal barrier synchronization within each domain, then performing an internal exchange phase within each domain, then performing an external barrier synchronization to synchronize between different domains, then performing an external exchange phase between the domains.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: June 1, 2021
    Assignee: GRAPHCORE LIMITED
    Inventors: Daniel John Pelham Wilkinson, Stephen Felix, Richard Luke Southwell Osborne, Simon Christian Knowles, Alan Graham Alexander, Ian James Quinn
  • Patent number: 11023236
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • Patent number: 11016773
    Abstract: Embodiments described herein provide for a computing device comprising a hardware processor including a processor trace module to generate trace data indicative of an order of instructions executed by the processor, wherein the processor trace module is configurable to selectively output a processor trace packet associated with execution of a selected non-deterministic control flow transfer instruction.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: May 25, 2021
    Assignee: INTEL CORPORATION
    Inventors: Salmin Sultana, Beeman Strong, Ravi Sahita
  • Patent number: 11010163
    Abstract: Disclosed herein is an apparatus which comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: May 18, 2021
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu, Subramaniam Maiyuran, Prasoonkumar Surti, Guei-Yuan Lueh, David Puffer, Supratim Pal, Eric J. Hoekstra, Travis T. Schluessler, Linda L. Hurd
  • Patent number: 11003620
    Abstract: An integrated circuit that is capable of performing sequence alignment via dynamic programming methods is provided. The integrated circuit may include a linear systolic array having series-connected processing engines, each of which has a n-stage deep pipeline. The systolic array may align first and second sequences, wherein the first sequence is divided into multiple segments equal to the internal depth of the pipeline. The systolic array may compute matrix scores for these segments in parallel until the entire sequence matrix score is computed. The internal pipeline structure and a loopback memory within the systolic array are configured to take care of any required data dependencies in the computation of the matrix scores.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Saurabh Patil, Srajudheen Makkadayil, Rekha Manjunath, Tarjinder Singh, Vikram Sharma Mailthody
  • Patent number: 10996953
    Abstract: A computer processing system is provided. The computer processing system includes a processor configured to execute a record form instruction cracked into two internal instructions. A first one of the two internal instructions executes out-of-order to compute a target register and a second one of the two internal instructions executes in-order to compute a condition register (CR) to improve a processing speed of the record form instruction.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian J. D. Barrick, Maarten J. Boersma, Niels Fricke, Michael J. Genden
  • Patent number: 10990569
    Abstract: A sorter sorts a list of elements using a plurality of registers. Each register stores a value of at most one element. Each register receives an input from a previous one of the registers indicating whether the previous one of the registers is storing a value of a list element before storing a value of a list element. Each register supplies an indication to a next register whether the register is storing a list element value. A register sends a stored value and the register identification to a register stack. The register stack uses the value as an index to store a pointer to the register. In that way a sorted list is created in the register stack. A register stores list location information for one or more occurrences of a value stored by the register. Overflow of list location information is handled in a duplicate values stack.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: April 27, 2021
    Assignees: AT&T INTELLECTUAL PROPERTY I, L.P., AT&T MOBILITY II LLC
    Inventors: Sheldon K. Meredith, William C. Cottrill
  • Patent number: 10990394
    Abstract: An integrated circuit may include a mixed instruction multiple data (xIMD) computing system. The xIMD computing system may include a plurality of data processors, each data processor representative of a lane of a single instruction multiple data (SIMD) computing system, wherein the plurality of data processors are configured to use a first dominant lane for instruction execution and to fork a second dominant lane when a data dependency instruction that does not share a taken/not-taken state with the first dominant lane is encountered during execution of a program by the xIMD computing system.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventor: Jeffrey L. Nye
  • Patent number: 10977042
    Abstract: A technique for using expedited RCU grace periods to avoid avoiding out-of-memory conditions for offloaded RCU callbacks. In an example embodiment, one or more processors in a computer system may be designated as no-callbacks (No-CBs) processors that do not perform read-copy update (RCU) callback processing. One or more RCU callback offload kernel threads (rcuo kthreads) may be spawned to perform RCU callback management for RCU callbacks generated by workloads running on the No-CBs processors. The rcuo kthreads may run on processors that are not No-CBs processors. The rcuo kthreads may perform RCU grace period waiting as part of their RCU callback management. The RCU grace period waiting may include selectively invoking either an RCU expedited grace period or waiting for a normal RCU grace period to elapse.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Paul E. McKenney
  • Patent number: 10977037
    Abstract: In one embodiment, a synchronization instruction causes a processor to ensure that specified threads included within a warp concurrently execute a single subsequent instruction. The specified threads include at least a first thread and a second thread. In operation, the first thread arrives at the synchronization instruction. The processor determines that the second thread has not yet arrived at the synchronization instruction and configures the first thread to stop executing instructions. After issuing at least one instruction for the second thread, the processor determines that all the specified threads have arrived at the synchronization instruction. The processor then causes all the specified threads to execute the subsequent instruction. Advantageously, unlike conventional approaches to synchronizing threads, the synchronization instruction enables the processor to reliably and properly execute code that includes complex control flows and/or instructions that presuppose that threads are converged.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: April 13, 2021
    Assignee: NVIDIA Corporation
    Inventors: Ajay Sudarshan Tirumala, Olivier Giroux, Peter Nelson, Jack Choquette
  • Patent number: 10963263
    Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Eran Shifer, Mostafa Hagog, Eliyahu Turiel
  • Patent number: 10963259
    Abstract: Implementing processor instrumentation in a processor pipeline includes determining a pipeline depth of each micro-operator for an instruction group used in an execution phase of the processor pipeline. The pipeline depth corresponds with a duration of execution, each micro-operator performs a type of functional operation in the execution phase, and the instruction group includes all the micro-operators required for the execution phase. A targeted micro-operator is identified for which the processor instrumentation is being performed, and the pipeline depth corresponding with the targeted micro-operator is used to determine and report a performance of the targeted micro-operator as part of the processor instrumentation. Problems indicated by the processor instrumentation are diagnosed and addressed based on the performance of the targeted micro-operator.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: March 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Avery Francois, Gregory William Alexander, Jonathan Ting Hsieh
  • Patent number: 10956361
    Abstract: A computing system includes a plurality of functional units, each functional unit having one or more inputs and an output. There is a shared memory block coupled to the inputs and outputs of the plurality of functional units. There is a private memory block assigned to each of the plurality of functional units. An inter functional unit data bypass (IFUDB) block is coupled to the plurality of functional units. The IFUDB is configured to route signals between the one or more functional units without use of the shared memory block.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Manoj Kumar, Pratap C. Pattnaik, Kattamuri Ekanadham, Jessica Tseng, Jose E. Moreira
  • Patent number: 10956164
    Abstract: A computer system includes a processor configured to generate a prediction by a branch predictor that a branch instruction will be taken or not taken by consulting a current state of a state machine, the state machine having at least one taken state and at least one not taken state. The processor is also configured to return the prediction to a processing unit and detect a result that the branch instruction was actually taken or actually not taken. The processor is further configured to, based on the prediction being different than the result or based on the prediction being weak and consistent with the result, consult a probability value being a static value and/or a value based on a history of outcomes of previous branch instructions, and based on the probability value having a selected value or being within a selected range, update the state machine.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Naga Gorti, Edmund Joseph Gieske
  • Patent number: 10956161
    Abstract: Provided is a method for predicting a target address using a set of Indirect Target TAgged GEometric (ITTAGE) tables and a target address pattern table. A branch instruction that is to be executed may be identified. A first tag for the branch instruction may be determined. The first tag may be a unique identifier that corresponds to the branch instruction. Using the tag, the branch instruction may be determined to be in a target address pattern table, and an index may be generated. A predicted target address for the branch instruction may be determined using the generated index and the largest ITTAGE table. Instructions associated with the predicted target address may be fetched.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Satish Kumar Sadasivam, Puneeth A. H. Bhat, Shruti Saxena