Patents Examined by Eric Coleman
  • Patent number: 11900108
    Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk, Martin G. Dixon, Sean P. Mirkes, Bret L. Toll, Maxim Loktyukhin, Mark C. Davis, Alexandre J. Farcy
  • Patent number: 11899613
    Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: February 13, 2024
    Inventors: Amrita Mathuriya, Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni
  • Patent number: 11886985
    Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: January 30, 2024
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Yuhwan Ro, Byeongho Kim, Jaehyun Park, Jungho Ahn, Minbok Wi, Sunjung Lee, Eojin Lee, Wonkyung Jung, Jongwook Chung, Jaewan Choi
  • Patent number: 11880684
    Abstract: Provided are a Reduced Instruction Set Computer-Five (RISC-V)-based artificial intelligence inference method and system. The RISC-V-based artificial intelligence inference method includes the following steps: acquiring an instruction and data of artificial intelligence inference by means of a Direct Memory Access (DMA) interface, and writing the instruction and the data into a memory; acquiring the instruction from the memory and translating the instruction, and loading the data from the memory to a corresponding register on the basis of the instruction; in response to the instruction being a vector instruction, processing, by a convolution control unit, corresponding vector data in a vector processing unit on the basis of the vector instruction; and feeding back the processed vector data to complete inference.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 23, 2024
    Inventor: Zhaorong Jia
  • Patent number: 11880683
    Abstract: Systems, apparatuses, and methods for efficiently processing arithmetic operations are disclosed. A computing system includes a processor capable of executing single precision mathematical instructions on data sizes of M bits and half precision mathematical instructions on data sizes of N bits, which is less than M bits. At least two source operands with M bits indicated by a received instruction are read from a register file. If the instruction is a packed math instruction, at least a first source operand with a size of N bits less than M bits is selected from either a high portion or a low portion of one of the at least two source operands read from the register file. The instruction includes fields storing bits, each bit indicating the high portion or the low portion of a given source operand associated with a register identifier specified elsewhere in the instruction.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: January 23, 2024
    Assignee: Advanced micro devices, inc.
    Inventors: Jiasheng Chen, Bin He, Yunxiao Zou, Michael J. Mantor, Radhakrishna Giduthuri, Eric J. Finger, Brian D. Emberling
  • Patent number: 11880682
    Abstract: Systems and methods are provided to perform multiply-accumulate operations of reduced precision numbers in a systolic array. Each row of the systolic array can receive reduced inputs from a respective reducer. The reduced input can include a reduced input data element and/or a reduced weight. The systolic array may lack support for inputs with a first bit-length and the reducers may reduce the bit-length of a given input from the first bit-length to a second shorter bit-length and provide the reduced input to the array. In order to reduce the bit-length, the reducer may reduce the number of trailing bits of the input. Further, the systolic array can receive a reduced and rounded input. The systolic array can propagate the reduced input through the processing elements in the systolic array. Each processing element may include a multiplier and/or an adder to perform arithmetical operations based on the reduced input.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: January 23, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Paul Gilbert Meyer, Thomas A Volpe, Ron Diamant, Joshua Wayne Bowman, Nishith Desai, Thomas Elmer
  • Patent number: 11874793
    Abstract: The present disclosure relates generally to multi-processor arrangements and, more particularly, to broadcast hubs for multi-processor arrangements. A processing tile may comprise a broadcast hub to obtain a plurality of parameters applicable in a particular operation from at least one of a plurality of processing tiles and initiate distribution of the plurality of parameters to the plurality of processing tiles, wherein the plurality of processing tiles may execute the particular operation based at least in part on the plurality of distributed parameters.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: January 16, 2024
    Assignee: Arm Limited
    Inventors: Erik Persson, Graeme Leslie Ingram, Rune Holm, John Wakefield Brothers, III
  • Patent number: 11868797
    Abstract: A method for processing virtualization of computers that are part of a group into virtual computers is provided. The method includes obtaining relationship data from the computers, where the relationship data identifies parameters used to communicate within the group. Then, the method analyzes utilization parameters for each of the computers of the group. A visual model for proposed virtualization of the group of computers is then generated. The visual model identifies hosting machines designated to define a virtual computer for each of the computers, where the visual model provides a graphical illustration of the group of computers once converted to virtual computers. The method enables adjustment of the proposed virtualization of the group of computers. Then, an execution sequence of virtualization operations to be carried out is generated, if execution of the proposed virtualization is triggered, and the execution sequence is saved to storage and accessed upon execution.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: January 9, 2024
    Assignee: VMware, Inc.
    Inventor: Abhinav Katiyar
  • Patent number: 11868774
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: January 9, 2024
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine
  • Patent number: 11853758
    Abstract: Techniques for decoupled access-execute near-memory processing include examples of first or second circuitry of a near-memory processor receiving instructions that cause the first circuitry to implement system memory access operations to access one or more data chunks and the second circuitry to implement compute operations using the one or more data chunks.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Berkin Akin, Alaa R. Alameldeen
  • Patent number: 11853754
    Abstract: Provided is a mask operation method for an explicit independent mask register in a GPU. The method comprises: each GPU hardware thread being able to access respective eight 128-bit-wide independent mask registers, which are recorded as $m0-$m7. With regard to mask operation instructions of the explicit independent mask register in the GPU, each hardware thread in the GPU is able to access respective eight 128-bit-wide independent mask registers, and four groups of mask operation instructions are available for a user, and respectively realize a reduction operation, an extension operation and a logic operation on the mask register, and data movement between the mask register and a general vector register.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: December 26, 2023
    Inventors: Chengxin Yin, Lei Wang
  • Patent number: 11853868
    Abstract: Embodiments of the present disclosure relate to a neural engine of a neural processor circuit having multiple multiply-add circuits and an accumulator circuit coupled to the multiply-add circuits. The multiply-add circuits perform multiply-add operations of a three dimensional convolution on a work unit of input data using a kernel to generate at least a portion of output data in a processing cycle. The accumulator circuit includes multiple batches of accumulators. Each batch of accumulators receives and stores, after the processing cycle, the portion of the output data for each output depth plane of multiple output depth planes. A corresponding batch of accumulators stores, after the processing cycle, the portion of the output data for a subset of the output channels and for each output depth plane.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: December 26, 2023
    Assignee: APPLE INC.
    Inventors: Christopher L. Mills, Sung Hee Park
  • Patent number: 11853756
    Abstract: A method includes receiving a request to modify a first value of a first field of a first item in a self-describing data system, and obtaining a domain comprising items in the self-describing data system. The first item and a second item are included in items, and the second item comprises a second field having a second value. The method includes calculating, based on a rule of the second field, a dependency of the second value on the first value. The rule specifies how the second value is to be calculated using the first value. The method includes modifying, based on the request, the first value. The method includes receiving an event triggered by the modification to the first value. The method includes, responsive to the event, calculating the second value based on the rule, and storing the second value in the second field.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: December 26, 2023
    Assignee: Aras Corporation
    Inventor: Sean Coleman
  • Patent number: 11853766
    Abstract: An example system includes memory; a central processing unit (CPU) to execute first operations; in-memory execution circuitry in the memory; and detector software to cause offloading of second operations to the in-memory execution circuitry, the in-memory execution circuitry to execute the second operations in parallel with the CPU executing the first operations.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Vy Vo, Dipanjan Sengupta, Mariano Tepper, Javier Sebastian Turek
  • Patent number: 11845452
    Abstract: An electronic control device includes a first processing control unit and a second processing control unit, wherein: the first processing control unit and the second processing control unit alternately start arithmetic processing with information of an external environment as an input; and second arithmetic processing of the second processing control unit is started after first arithmetic processing by the first processing control unit is started and before the first arithmetic processing is ended.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: December 19, 2023
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Taisuke Ueta, Tatsuya Horiguchi, Kenichi Shimbo, Hideyuki Sakamoto
  • Patent number: 11847452
    Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: December 19, 2023
    Assignee: Intel Corporation
    Inventors: Menachem Adelman, Robert Valentine, Zeev Sperber, Mark J. Charney, Bret L. Toll, Rinat Rappoport, Jesus Corbal, Dan Baum, Alexander F. Heinecke, Elmoustapha Ould-Ahmed-Vall, Yuri Gebil, Raanan Sade
  • Patent number: 11842193
    Abstract: An arithmetic device includes an arithmetic circuit configured to perform an arithmetic operation to output arithmetic result data and a data output unit configured to feedback bias data to the arithmetic circuit prior to the arithmetic operation.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: December 12, 2023
    Assignee: SK hynix Inc.
    Inventor: Choung Ki Song
  • Patent number: 11836493
    Abstract: Embodiments for providing memory access operations for graph analytics by a processor are disclosed. An entire chunk of load and store instructions may be atomically and concurrently executed, where the entire chunk of the load and store instructions are delineated from a plurality of alternative load and store instructions.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: December 5, 2023
    Inventors: Manoj Kumar, Gianfranco Bilardi, Kattamuri Ekanadham, Jose E. Moreira, Pratap C. Pattnaik, Jessica Hui-Chun Tseng
  • Patent number: 11829321
    Abstract: A systolic array cell is described, the cell including two general-purpose arithmetic logic units (ALUs) and register-file. A plurality of the cells may be configured in a matrix or array, such that the output of the first ALU in a first cell is provided to a second cell to the right of the first cell, and the output of the second ALU in the first cell is provided to a third cell below the first cell. The two ALUs in each cell of the array allow for processing of a different instruction in each cycle.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: November 28, 2023
    Assignee: Google LLC
    Inventors: Reginald Clifford Young, Trevor Gale, Sushma Honnavara-Prasad, Paolo Mantovani
  • Patent number: 11829323
    Abstract: Disclosed in some examples, are methods, systems, programmable atomic units, and machine-readable mediums that provide an exception as a response to the calling processor. That is, the programmable atomic unit will send a response to the calling processor. The calling processor will recognize that the exception has been raised and will handle the exception. Because the calling processor knows which process triggered the exception, the calling processor (e.g., the Operating System) can take appropriate action, such as terminating the calling process. The calling processor may be a same processor as that executing the programmable atomic transaction, or a different processor (e.g., on a different chiplet).
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: November 28, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Tony Brewer