Abstract: A semiconductor device having in a semiconductor body a Darlington amplifier comprising a vertical enhancement VMOS-transistor (T.sub.1) as input transistor and a vertical bipolar power transistor (T.sub.2) as output transistor. In order to increase the switching speed, a lateral enhancement MOS transistor (T.sub.3) of complementary conductivity type to the first transistor (T.sub.1) is connected in parallel with the emitter-base junction of the bipolar output transistor (T.sub.2). The gate electrodes of the first and second transistors are interconnected and associated with an input terminal E. Double and treble epitaxial layer structures are disclosed for integrating the device in the semiconductor body. The lateral third transistor (T.sub.3) may be provided either within or outside the area of an epitaxial layer forming the emitter zone of the second transistor (T.sub.2).

Abstract: The unique initial masking step is used in a method of more predictably and uniformly spacing features on a surface of a semiconductor device by combining it with two dielectric maskants. A unique semiconductor device masking is claimed in which semiconductor device features are initially spaced by means of pitch, i.e. line and a contiguous space, instead of just a line in the initial masking.

Abstract: Lateral FET structure is disclosed for bidirectional power switching, including AC application. A plurality of integrated FETs each have left and right source regions and left and right channel regions with a common drift region therebetween, and conduct current in either direction according to the polarity of main terminals. Gating means includes gate electrode means disposed proximate and insulated from the channel regions and adapted for storing trapped charge tunneled through an insulated layer from a charging electrode.

Abstract: Optical-to-electrical conversion is accomplished using an undoped region bounded by a tunneling junction of the order of the mean free path of an electron. A number of regions are assembled in series with larger thickness away from the light incident surface. The thickness and doping of the regions for maximum effectiveness in monochromatic light are tailored to produce similar quantities of carriers from the light. A nine section GaAs structure with 50 .ANG. n.sup.+ and p.sup.+ tunneling bounding regions has a 90% quantum efficiency and delivers a 5 volt output with a 0.35 picosecond transit time.

Abstract: Planar junction Josephson interferometer in which the junctions (24) are "buried" underneath the interferometer bridge (27) connecting the junction counter-electrodes (25). The insulation (26) that separates the common base electrode (22) from the bridge (27) is extended between the bridge and the upper surfaces of the counter-electrodes. This design permits, without decreasing the interferometer loop inductance, a reduction of the interferometer area and thus results in a higher packaging density in logic or memory applications.The buried junction concept can be applied in symmetric or asymmetric interferometer designs with virtually any number of junctions, any type of input current control or current feeding scheme.The interferometer can be produced using conventional evaporation, photo-resist, and etch processes based on optical lithography. Further area reduction is achieved in applying e-beam or x-ray technology.

Abstract: Optical-to-electrical logic operations may be performed employing as each logic variable a different light wavelength and providing an optical-to-electrical semiconductor converter such that each particular wavelength responsive optical energy receiving region is an updoped region bounded by a thin tunneling junction having a thickness of the order of the mean free path of a carrier in the tunneling region.