Abstract: A silicon wafer is heated from an initial pre-heating temperature (T0) up to a first annealing temperature (T1) by a rapid heating up step using an IR lamp. A first annealing is executed at the first annealing temperature (T1). Successively, while the silicon wafer is maintained at a second annealing temperature (T2) lower than the first annealing temperature (T1), a second annealing step is executed by a resistive heating furnace. A thermal oxidation can be executed as the second annealing step. To do so, an equipment for manufacturing a semiconductor device in the present invention is provided with: a heating device having an IR lamp and a resistive heater; an annealing tube having on a surface thereof a plurality of concave portions in such a way that each bottom approaches a central line; a resistive heater wrapped around this annealing tube; and an IR lamp movably inserted into and pulled out from the concave portion from the external.

Abstract: The present invention relates to the fabrication of semiconductor devices and more particularly to a new method for avoiding abnormal via holes when Spin On Glass, SOG, is used as a means of planarizing an interlevel metal interconnect structure. The invention addresses the problem of locations of micro bubbles in a SOG layer that can lead to seams, voids and a ragged surface topology which, in turn, can make it very difficult to eventually etch well formed via holes at such locations. The invention details a new etch back method that solves the above problem by properly smoothing the micro bubble locations. This new method includes a sequence of anisotropic and isotropic etching steps that are used to partially etch back the cured SOG layer in order to achieve a planarized surface while also smoothing the micro bubble locations in the cured SOG layer.