Abstract: In a monolithic active matrix circuit that uses offset-gate TFTs in which the gate electrode is offset from the source and drain regions or TFTs whose gate insulating film is formed by vapor deposition, not only an active matrix circuit but also a drive circuit therefor is formed by using P-channel TFTs.

Abstract: A conductive layer which is formed on an insulative layer on a semiconductor substrate is connected to the semiconductor substrate via a through portion which passes through the insulative layer and reaches the semiconductor substrate. In a state where the conductive layer is electrically connected to the semiconductor substrate via the through portion, a patterning process using a plasma etching is performed on the conductive layer, thereby forming a conductive path. After the formation of the conductive path, a heating process is performed on the substrate or the conductive path in order to disconnect the electrical connection between the through portion and the substrate by a reaction between the through portion and the semiconductor substrate which is in contact therewith.

Abstract: A method of removing HDP oxide deposition comprises the steps of: (1) etching the HDP oxide deposition by in-side-out model, wherein the etching rate in the center of the substrate is faster than the edges of the substrate; (2) etching the HDP oxide deposition by out-side-in model, wherein the etching rate in the edges of the substrate is faster than the center of the substrate; and (3) removing the remaining silicon oxide layer using chemical-mechanical polishing (CMP). According to the method of the invention, the HDP oxide deposition can be planarized more uniform.

Abstract: In a semiconductor layer formed on a first insulating film is formed an element isolation groove extending to the first insulating film. Thereafter, a second insulating film is deposited in the element isolation groove by using a vapor deposition method.

Abstract: Method for determining the location of a droplet of liquid placed on a surface of a semiconductor wafer. In one embodiment the method includes establishing first and second reference axes that intersect at a point and superimposing the point over the droplet on the semiconductor wafer surface. A first reference coordinate indicative of the position of the point along the first axis and a second reference coordinate indicative of the position of the point along the second axis are generated.

Abstract: A method for improving high-&kgr; gate dielectric film (104) properties. The high-&kgr; film (104) is subjected to a two step anneal sequence. The first anneal is a high temperature anneal in a non-oxidizing ambient (106) such as N2 to densify the high-&kgr; film (104). The second anneal is a lower temperature anneal in an oxidizing ambient (108) to perform a mild oxidation that heals the high-&kgr; film and reduces interface defects.

Abstract: The present invention relates to a semiconductor device in which a barrier insulating film is formed to cover a copper film or a wiring consisting mainly of the copper film. The barrier insulating film is a structure of two or more layers including at least a first barrier insulating film containing silicon, oxygen, nitrogen and hydrogen or silicon, oxygen, nitrogen, hydrogen and carbon, and a second barrier insulating film containing silicon, oxygen and hydrogen or silicon, oxygen, hydrogen and carbon.

Abstract: A semiconductor device is provided which avoids lowering of the sense speeds of plural sense amplifiers due to their drives. In the semiconductor device, a P-type well layer (6) containing a P-type impurity is selectively disposed in a main surface of an epitaxial layer (3). An N-type bottom layer (7) containing an N-type impurity is disposed so as to make contact with a bottom surface of the P-type well layer (6). A P-type well layer (2) is disposed in such a thickness as to make contact with the N-type bottom layer (7), so that the N-type bottom layer (7) and P-type well layer (2) form a PN junction. Further, in the main surface of the epitaxial layer (3), an N-type well layer (4) containing an N-type impurity and a P-type well layer (5) containing a P-type impurity are selectively disposed so as to sandwich therebetween the P-type well layer (6).

Abstract: In a process for forming a silicon-based film on a substrate according to the present invention, the substrate has a temperature gradient in the thickness direction thereof in the formation of the silicon-based film and the temperature gradient is made such that a deposition surface of the substrate has a higher temperature than a backside or the direction of the temperature gradient is reversed. With this configuration, the present invention provides a silicon-based thin film having good properties at a high deposition rate and provides a semiconductor device including it. The present invention also provides a semiconductor device including the silicon-based thin films that has good adhesion and weather-resisting properties and that can be manufactured in a short tact time.

Abstract: A method of reducing by-product deposition inside wafer processing equipment includes providing a chamber having a peripheral inner wall and placing a semiconductor wafer within the chamber. The method also includes placing a ring within the chamber proximate the peripheral inner wall and introducing a plurality of reactant gases into the chamber and reacting the gases. The method also includes introducing a heated gas into the chamber through the ring proximate the peripheral inner wall to increase the temperature of the peripheral inner wall.

Abstract: A method and process sequence for accurately aligning (die to interconnect metal on flex substrate such as polyimide flex is described. A mask for via formation is first patterned in a metal layer on the bottom surface of the flex substrate. Die attach means such as die attach adhesive is then applied to the top side of flex substrate. The bond pads on die are locally, adaptively aligned to the patterned metal via mask on the flex with high accuracy. Vias down to the die bond pads are then created by either plasma etching or excimer laser ablation through the existing aligned metal mask on the flex substrate, and interconnect metal is then deposited, patterned and etched. As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using “adaptive lithography”. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost.

Abstract: A process for filling a polysilicon seam. First, a semiconducting substrate or an insulating layer having a trench is provided, and a first polysilicon layer having a seam is filled in the trench. Next, the first polysilicon layer is etched to expose the seam. Next, a second polysilicon layer is formed to fill the top portion of the seam and close the seam.

Abstract: A temperature measuring apparatus, comprises a light splitting section for splitting the light radiated from a substrate into plural light components having wavelengths over a predetermined wavelength region, a detection section for detecting the intensities of the light components obtained by the light splitting section, an integrated value calculating section for calculating an integrated value of radiation intensity by cumulatively adding the intensities of the light components detected by the detecting section, and a surface temperature calculating section for calculating the surface temperature of the substrate from the integrated value, on the basis of reference data representing the relation between the temperature and the integrated value.

Abstract: A method of integrating a polymeric interlayer dielectric. The method comprises forming a dielectric layer comprising a polymer on a conductive layer formed on a substrate. A sacrificial hard mask is then formed on the dielectric layer. A first photoresist layer is then patterned on the sacrificial hard mask to define a first etched region, which is formed through the dielectric layer while substantially all of the first photoresist layer is removed. A sacrificial fill layer then covers the sacrificial hard mask and fills the first etched region. A second photoresist layer is patterned over the sacrificial fill layer to define a second etched region which is formed through the sacrificial fill layer and the dielectric layer while substantially all of the second photoresist layer and the sacrificial fill layer are simultaneously removed.

Abstract: When contact holes are concurrently formed in an inter-level insulating layer over an impurity region in a silicon substrate and a polycide line on a thick field oxide layer, the manufacturer interrupts the etching at the refractory metal silicide layer of the polycide line, and restarts the etching after removal of a part of the refractory metal silicide layer exposed to the short contact hole, thereby preventing the impurity region from undesirable etching for the refractory metal silicide layer.

Abstract: A method for producing a semiconductor substrate of the present invention, includes the steps: forming a first patterned mask containing a material having a growth suppressing effect on a lower substrate; growing a semiconductor crystal on the lower substrate via the first patterned mask to form a first semiconductor crystal layer; forming a second patterned mask containing a material having a growth suppressing effect on or above the lower substrate, the second patterned mask at least having a surface which is positioned at a level different from a level of a surface of the first patterned mask, with respect to a surface of the lower substrate; and growing a semiconductor crystal on or above the lower substrate via the second patterned mask to form a second semiconductor crystal layer.

Abstract: Structures and processes are disclosed for reducing electrical contact resistance between two metal layers. Specifically, a resistive aluminum oxide layer forms spontaneously on metal lines including aluminum, within a V-shaped contact via which is opened in an insulating layer through a mask. The mask includes an opening with a width of less than about 0.75 &mgr;m. After removing the mask, the via is treated with an RF etch. The resultant contact has a width at the bottom of less than 0.9 &mgr;m. A titanium layer of 300 Å to 400 Å is deposited into the via, with about 60 Å to 300 Å reaching the via bottom and reacted with the underlying aluminum. The reaction produces a titanium-aluminum complex (TiAlx) with a thickness of about 150 Å to 900 Å. Advantageously, this composite layer provides a low resistivity contact between the aluminum-containing layer and a subsequently deposited metal layer.

Abstract: A semiconductor wafer (10), a method of providing information on a semiconductor wafer (10), a system of semiconductor wafer (10) and reading means, and a method of reading information from a semiconductor wafer (10) are provided. The invention is characterized by magnetic means (14) as information carrier and the respective magnetic sensors (26) to read such information.

Abstract: A current mirror circuit is described which includes a current input terminal (14A), a current output terminal (14B) and a common terminal (14C). A first controllable semiconductor element (T1) is arranged between the current input terminal (14A) and the common terminal (14C). A second controllable semiconductor element (T2) is arranged between the current output terminal (14B) and the common terminal (14C). The controllable semiconductor elements (T1, T2) have interconnected control electrodes (T1A, T2A) which are also coupled to a bias voltage source (VBIAS), for biasing said control electrodes at a reference voltage. The circuit further includes a transconductance stage (12) with an input (12A) coupled to the current input terminal (14A) and an output (12B) coupled to the common terminal (14C). The control electrodes (T1A, T2A) are coupled to the common terminal (14C) via a third controllable semiconductor element (T3).

Abstract: A defect-free film is formed on a surface of a protrusive electrode. An immersion Au film is formed on the surface of the protrusive electrode, after a gap which an immersion Au plating liquid can enter evenly is formed between a protrusive electrode made of Ni or a Ni alloy on an electrode pad made of Al or mainly made of Al and a protective coat by etching.