Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

Abstract: Painted circuit devices, methods, and systems are disclosed. In some implementations, painted circuit devices are created using multiple layers of electrically conductive paint. In one aspect, a painted circuit includes a substrate and one or more paint layer applied to the substrate, where the one or more paint layers each form an electrical component of the painted circuit. A given paint layer of the one or more paint layers can include a conductive paint formulation having a resistance that is defined by a concentration of conductive material that is included in the conductive paint formulation and a thickness of the given paint layer, and lower concentrations of the conductive material included in the conductive paint formulation provide a higher resistance than higher concentrations of conductive material.

Abstract: An organic EL display device 1 includes: an organic EL element 4 provided above an element substrate 10; and a sealing film 2 formed above the element substrate 10 so as to cover the organic EL element 4, and made of silicon nitride (SiNx). The sealing film 2 is comprised of a first sealing layer 25, a second sealing layer 26 provided on the surface of the first sealing layer 25, and a third sealing layer 27 provided on the surface of the second sealing layer 26. This organic EL display device 1 is characterized in that a ratio of an SiN-group content to an NH-group content is higher in the first and third sealing layers 25 and 27 than in the second sealing layer 26 based on the absorption area ratio determined by FT-IR measurement.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: an Nth metal layer; a bottom electrode over the Nth metal layer; a magnetic tunneling junction (MTJ) over the bottom electrode; a top electrode over the MTJ; a spacer, including: a first spacer layer including SiN with a first atom density, the first spacer layer laterally encompassing the MTJ; and a second spacer layer including SiN with a second atom density different from the first atom density, the second spacer layer laterally encompassing at least a portion of the first spacer layer; and an (N+1)th metal layer over the top electrode. A method for manufacturing a semiconductor structure is also disclosed.

Abstract: A vertical FET with asymmetrically positioned source region and drain region is provided. The source region of the vertical FET is separated from a gate electrode by a gate dielectric and the drain region of the vertical FET is separated from the gate electrode by a drain spacer formed therebetween.

Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure, in which the first spacer has a top portion and a bottom portion between the top portion and the substrate. The source/drain structure is present adjacent to the bottom portion of the first spacer. The conductor is electrically connected to the source/drain structure. The protection layer is present at least between the conductor and the top portion of the first spacer. The contact etch stop layer is present at least partially between the conductor and the bottom portion of the first spacer while absent between the protection layer and the top portion of the first spacer.

Abstract: A light emitting diode including a first light emitting cell and a second light emitting cell separated from each other on a substrate, a first transparent electrode layer electrically connected to the first light emitting cell, an interconnection electrically connecting the first light emitting cell to the second light emitting cell, and a first insulation layer. The first transparent electrode layer is disposed on an upper surface of the first light emitting cell and partially covers a side surface of the first light emitting cell. The first insulation layer separates the first transparent electrode layer from the side surface of the first light emitting cell, and includes an opening to expose a lower semiconductor layer of the first light emitting cell.

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

Abstract: A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device.

Abstract: At the time of removing a flexible organic electroluminescence display device from a support substrate, delamination is prevented from occurring at a laminate structure of an OLED. The organic electroluminescence display device includes a flexible base material, a plurality of organic electroluminescence elements, each comprising a pixel electrode, a reflective layer that is disposed between the base material and the pixel electrode and reflects light, a semitransparent counter electrode that is disposed on a light-emitting surface side with respect to the pixel electrode, and an organic electroluminescence function layer that is a lamination including an organic light-emitting layer and disposed between the pixel electrode and the counter electrode, a transparent electrode laminated on the counter electrode, an organic film laminated on the transparent electrode 80, and a gap 84 generated at a part of an interface between the transparent electrode 80 and the organic film 82.

Abstract: A trench having a uniform depth is provided in an upper portion of a semiconductor substrate. A continuous dielectric material layer is formed, which includes a gate dielectric that fills an entire volume of the trench. A gate electrode is formed over the gate dielectric such that the gate electrode overlies a center portion of the gate dielectric and does not overlie a first peripheral portion and a second peripheral portion of the gate dielectric that are located on opposing sides of the center portion of the gate dielectric. After formation of a dielectric gate spacer, a source extension region and a drain extension region are formed within the semiconductor substrate by doping respective portions of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate comprising an upper layer portion, a first insulating member located in the upper layer portion of the semiconductor substrate and having one or more corner portions, an electrode located on the semiconductor substrate, wherein the electrode overlies at least one of the corner portions of the first insulating member, and an insulating film located between the semiconductor substrate and the electrode.

Abstract: A semiconductor device includes a semiconductor substrate including a first source/drain region formed in an upper portion of the semiconductor substrate, a metal silicide layer that covers a top surface of the first source/drain region, and a semiconductor pillar that penetrates the metal silicide layer and is connected to the semiconductor substrate. The semiconductor pillar includes a second source/drain region formed in an upper portion of the semiconductor pillar, a gate electrode on the metal silicide layer, with the gate electrode surrounding the semiconductor pillar in a plan view. A contact is connected to the metal silicide layer.

Abstract: Semiconductor device assemblies having stacked semiconductor dies and electrically functional heat transfer structures (HTSs) are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a mounting surface with a base region and a peripheral region adjacent the base region. At least one second semiconductor die can be electrically coupled to the first semiconductor die at the base region. The device assembly can also include an HTS electrically coupled to the first semiconductor die at the peripheral region.

Abstract: A display device includes a base, an organic light-emitting element including a stacked structure that has a first electrode layer, an organic light-emitting layer, and a second electrode layer that are stacked in order on the base, a drive element that is provided on the base, and drives the organic light-emitting element, and an auxiliary electrode layer provided on the base, and including an end surface that is in contact with the second electrode layer.

Abstract: Devices and methods of fabricating integrated circuit devices for dynamically applying bias to back plates and/or p-well regions are provided. One method includes, for instance: obtaining a wafer with a silicon substrate, at least one first oxide layer, at least one silicon layer, and at least one second oxide layer; forming at least one recess in the wafer; depositing at least one third oxide layer over the wafer and filling the at least one recess; depositing a silicon nitride layer over the wafer; and forming at least one opening having sidewalls and a bottom surface within the filled at least one recess. An intermediate semiconductor device is also disclosed.

Abstract: The present invention relates to a composition for an insulator of a thin film transistor, an insulator and an organic thin film transistor comprising the same. The insulator of a thin film transistor prepared with the composition of the present invention displays an excellent permittivity along with a low surface energy, and the organic thin film transistor comprising the same displays an improved organic semiconductor morphology formed on the top surface of the insulator, so that it can bring the effect of reducing leakage current density, improving charge carrier mobility, and improving current on/off ratio.

Abstract: The present disclosure relates to a solid-state imaging element in which the cost reduction of a curved imaging element can be achieved, a method for manufacturing the solid-state imaging element, and an electronic apparatus. A curvature base is formed so as to be curved in a concave shape at a center leaving a small edge. The curvature base is divided into five portions of an element disposition portion and four peripheral portions. This element disposition portion is formed in a porous state. A pore (air bubble) in the porous state is smaller than a pixel size. A porous material such as a ceramic-based material, a metal-based material, or a resin-based material can be used as the porous material, for example. The present disclosure can be applied to a CMOS solid-state imaging element to be used for an imaging device, for example.

Abstract: A method of fabricating tantalum nitride barrier layer in an ultra low threshold voltage semiconductor device is provided. The method includes forming a high-k dielectric layer over a semiconductor substrate. Subsequently, a tantalum nitride barrier layer is formed on the high-k dielectric layer. The tantalum nitride barrier layer has a Ta:N ratio between 1.2 and 3. Next, a plurality of first metal gates is formed on the tantalum nitride barrier layer. The first metal gates are patterned, and then a second metal gate is formed on the tantalum nitride barrier layer.

Abstract: A display device includes: a base substrate including a pixel area at which an image is displayed; a light blocking pattern on the base substrate; a thin film transistor on the light blocking pattern; a gate line connected to the thin film transistor and lengthwise extending in a first direction; a data line connected to the thin film transistor and lengthwise extending in a second direction; and a pixel electrode in the pixel area and spaced apart from the gate line in the second direction. The light blocking pattern includes: a first light blocking pattern lengthwise extending in the first direction; and a second light blocking pattern overlapping the thin film transistor. The first light blocking pattern overlaps the gate line and the pixel electrode spaced apart from each other in the second direction.