Abstract: A method, a device, and a bus system for synchronizing at least two TTCAN buses having at least one bus user, a global time being determined in each TTCAN bus, and the deviations in the global times of the TTCAN buses being determined from the global times, the TTCAN buses being connected via at least one user and the deviations in the individual global times being transmitted to at least one bus user, and the global times of the TTCAN buses connected via at least one user being adjusted to one another as a function of the deviations in the global times, so that the TTCAN buses are synchronized with respect to the global times.

Abstract: An output clock for a memory device having a read latency more than one clock cycle includes a clock generator at a central location on the device. A clock channel couples the clock generator to output structures. A timing path emulates the address/data paths in the memory, and is responsive to an address emulation signal produced by the clock generator to provide dummy data near the output structures. An output clock signal with an adjustable phase and a dummy data reference clock signal on the input of the clock channel are generated. A phase detector near the output structures, determines whether the output clock is early, late or on time with respect to the dummy data. Logic signals are produced at the phase detector, and returned to the clock generator for adjusting the relative phase of the output clock signal.

Abstract: An image processing apparatus including an image processing circuit, a frequency dispersion circuit, and a timing signal generator. The image processing circuit processes an image signal, and the frequency dispersion circuit performs frequency dispersion relative to a reference clock signal by continuously modulating an oscillating frequency of the reference clock signal in a predetermined modulation cycle and to generate a frequency dispersion clock signal. The timing signal generator generates a timing signal that controls an operation of the image processing circuit using the frequency dispersion clock signal, in synchronism with the predetermined modulation cycle used for the frequency dispersion.