Abstract: A method for producing a gallium nitride crystal includes growing a gallium nitride crystal 5 by dissolving nitrogen in a mixed melt including gallium and sodium, and collecting the gallium 55 separated from an alloy 51 including the gallium and the sodium by reacting the alloy 51 and a liquid 52 that ionizes the sodium and separating sodium ions and the gallium 55 from the alloy.

Abstract: A method for growing a silicon single crystal by a Czochralski method, includes: conducting preliminary examination of growth conditions under which crystal collapse does not occur, the preliminary examination being based on a correlation between presence or absence of the crystal collapse in the silicon single crystal and a position at which an internal stress in the crystal when the silicon single crystal is grown will exceed a prescribed threshold, the position being away from a crystal growth interface; and growing the silicon single crystal in accordance with the growth conditions under which the crystal collapse does not occur, the growth conditions being determined from the preliminary examination. The method can grow a silicon single crystal while crystal collapse is effectively prevented.

Abstract: A method of producing a double-doped scintillation crystal is provided. Czochralski method is used to grow a double-doped single crystal boule. The double-doped single crystal boule is a single crystal boule of rare-earth silicate double-doped with cerium (Ce) and calcium (Ca) or magnesium (Mg). The double-doped single crystal boule is subjected to a thermal annealing process in a furnace. A yield of pixel samples of the double-doped scintillation crystal is improved after a processing process, and the present invention achieves low producing cost, high yield, less crystal fragmentations, high luminescence intensity and short decaying time.

Abstract: A method of fabricating a bridge beam of an inkjet printhead employs a cavity formed under the bridge beam and an etch-stop layer that limits a back-surface recess formation. The method includes forming a cavity that connects between a bottom of a pair of trenches in and extending from a front surface of a substrate and depositing an etch-stop layer at a bottom of the cavity. The method further includes forming a recess in a back surface of the substrate, the recess exposing the etch-stop layer and the etch-stop layer limiting a depth of the formed recess. The method further includes removing the exposed etch-stop layer to connect the cavity and the recess, the bridge beam being a portion of the substrate above the formed cavity and between the trenches.

Abstract: A method for manufacturing a planar optical waveguide device of which a core includes a plurality of alternatively arranged fin portions and valley portions to form a grating structure, in which the core widths of the valley portions vary along the longitudinal direction, the method including: a high refractive index material layer forming step of forming a high refractive index material layer; a photoresist layer forming step of forming a photoresist layer on the high refractive index material layer; a first exposure step of forming shaded portions on the photoresist layer using a phase-shifting photomask; a second exposure step of forming shaded portions on the photoresist layer using a binary photomask; a development step of developing the photoresist layer; and an etching step of etching the high refractive index material layer using the photoresist pattern resulted from the development step.

Abstract: In order to prevent occurrence of a residual film distribution dependent upon a pattern density of a mold, in producing the mold to be used for imprint lithography, by etching using a mask, use is made of a first mask M1 for forming a desired pattern to be formed on a surface of the mold, and a second mask M2 for partially covering the first mask such that the area covering openings of the first mask is made larger as an opening ratio of the pattern formed on the first mold surface is higher, thereby to make a volume of a recess of the mold in a given area; in which, after the mold is etched by the first mask, etching is further conducted by covering partially the first mask with the second mask without removing the first mask; or alternatively, the etching is conducted with the first mask and the second mask overlapped from the beginning, thereby to use the second mask as a mask for delaying the etching, for conduct the etching.

Abstract: The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first dry etching process to a semiconductor substrate in an etch chamber through openings of a patterned mask layer defining gate regions, removing a polysilicon layer and a metal gate layer on the semiconductor substrate; applying a H2O steam to the semiconductor substrate in the etch chamber, removing a capping layer on the semiconductor substrate; applying a second dry etching process to the semiconductor substrate in the etch chamber, removing a high k dielectric material layer; and applying a wet etching process to the semiconductor substrate to remove polymeric residue.

Abstract: The present invention relates to processes involving contacting articles that include titanium or titanium alloy with a solution comprising hydrochloric acid and chloride-containing compound for a time and at a temperature effective to form a plurality of indentions that, independently, have a diameter of from about 200 nm to 10 microns.

Abstract: A method for fabricating a semiconductor device with improved bonding ability is disclosed. The method comprises providing a substrate having a front surface and a back surface; forming one or more sensor elements on the front surface of the substrate; forming one or more metallization layers over the front surface of the substrate, wherein forming a first metallization layer comprises forming a first conductive layer over the front surface of the substrate; removing the first conductive layer from a first region of the substrate; forming a second conductive layer over the front surface of the substrate; and removing portions of the second conductive layer from the first region and a second region of the substrate, wherein the first metallization layer in the first region comprises the second conductive layer and the first metallization layer in the second region comprises the first conductive layer and the second conductive layer.

Abstract: The invention provides an etching method for realizing trench etching without causing any damages to the side walls of the trench while maintaining a high-etching rate. The plasma etching method relates to forming a groove or a hole by forming a silicon trench to a silicon substrate or a silicon substrate having a silicon oxide dielectric layer via a mixed gas plasma containing a mixed gas of SF6 and O2 or a mixed gas of SF6, O2 and SiF4 and having added thereto a gas containing hydrogen within the range of 5 to 16% (percent concentration) of the total gas flow rate of the mixed gas.

Abstract: An assembly including a main wafer having a body with a front side and a back side and a plurality of blind electrical vias terminating above the back side, and a handler wafer, is obtained. A step includes exposing the blind electrical vias to various heights on the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side.

Abstract: The invention provides chemical-mechanical polishing (CMP) compositions and methods for polishing a silicon-containing substrate. A method of the invention comprises the steps of contacting a silicon-containing substrate with a polishing pad and an aqueous CMP composition, and causing relative motion between the polishing pad and the substrate while maintaining a portion of the CMP composition in contact with the surface of the substrate to abrade at least a portion of the substrate. The CMP composition comprises a ceria abrasive, a polishing additive bearing a functional group with a pKa of about 4 to about 9, a nonionic surfactant with an hydrophilic portion and a lipophilic portion wherein the hydrophilic portion has a number average molecular weight of about 500 g/mol or higher, and an aqueous carrier, wherein the pH of the composition is 7 or less. The method reduces defects on the wafers, particularly local areas of high removal.

Abstract: A magnetic head includes a pole layer, and an encasing layer having a groove that accommodates the pole layer. A manufacturing method for the magnetic head includes the steps of forming a nonmagnetic layer that will later undergo formation of the groove therein and will thereby become the encasing layer; forming the groove in the nonmagnetic layer so that the nonmagnetic layer becomes the encasing layer; and forming the pole layer such that the pole layer is accommodated in the groove of the encasing layer. The nonmagnetic layer is formed of Al2O3. The step of forming the groove in the nonmagnetic layer includes the step of taper-etching the nonmagnetic layer by reactive ion etching with an etching gas containing at least BCl3 and N2 among BCl3, Cl2 and N2.

Abstract: A method of patterning a metal layer includes forming a first mask on a surface of the metal layer, the first mask having an opening through the first mask that exposes the metal layer, and forming a nanogap in the exposed metal layer using an ion beam directed through the opening. The first mask limits a lateral extent of the ion beam, and the nanogap has a width that is less than a width of the opening.

Abstract: A method of manufacturing a substrate for a liquid discharge head having a silicon substrate in which a liquid supply port is provided includes providing the silicon substrate, an etching mask layer having an aperture being formed on one surface of the silicon substrate, forming a region comprising an amorphous silicon in the interior of the silicon substrate by irradiating the silicon substrate with laser light, forming a recess, which has an opening at a part of a portion exposed from the aperture on the one surface, from the one surface of the silicon substrate toward the region, and forming the supply port by performing etching on the silicon substrate in which the recess and the region have been formed from the one surface through the aperture of the etching mask layer.

Abstract: A flat panel display and a method of manufacturing the same are disclosed. In one embodiment, the manufacturing method includes: i) preparing a substrate, ii) forming a plurality of subpixels on the substrate and iii) forming a light resonating layer including two or more layers on the subpixels, wherein the light resonating layer varies in thickness depending on the subpixels. According to at least one embodiment, it is possible to improve the brightness and the external light coupling efficiency. Further, it is possible to easily manufacture the light resonating layer with the structure in which the low refractive layers alternate with the high refractive layers.

Abstract: A substrate processing method that can eliminate unevenness in the distribution of plasma. The method is for a substrate processing apparatus that has a processing chamber in which a substrate is housed, a mounting stage that is disposed in the processing chamber and on which the substrate is mounted, and an electrode plate that is disposed in the processing chamber such as to face the mounting stage, the electrode plate being made of silicon and connected to a radio-frequency power source, and carries out plasma processing on the substrate. In the plasma processing, the temperature of the electrode plate is measured, and based on the measured temperature, the temperature of the electrode plate is maintained lower than a critical temperature at which the specific resistance value of the silicon starts changing.

Abstract: A method of detecting substrate arcing in a semiconductor plasma processing apparatus is provided. A substrate is placed on a substrate support in a reaction chamber of a plasma processing apparatus. Process gas is introduced into the reaction chamber. A plasma is generated from the process gas and the substrate is processed with the plasma. Intensities of real-time spectrometry signals of selected gas species produced in the reaction chamber during plasma processing are monitored. The selected gas species are generated by a substrate arcing event. The arcing event is detected when the intensities are above a threshold value.

Abstract: A method of semiconductor fabrication including an etching process is provided. The method includes providing a substrate and forming a target layer on the substrate. An etchant layer is formed on the target layer. The etchant layer reacts with the target layer and etches a portion of the target layer. In an embodiment, an atomic layer of the target layer is etched. The etchant layer is then removed from the substrate. The process may be iterated any number of times to remove a desired amount of the target layer. In an embodiment, the method provides for decreased lateral etching. The etchant layer may provide for improved control in forming patterns in thin target layers such as, capping layers or high-k dielectric layers of a gate structure.

Abstract: Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl3, and a pH adjuster.