Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.
Type:
Grant
Filed:
October 30, 2019
Date of Patent:
September 7, 2021
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Inventors:
Chung-Yen Chou, Fu-Ting Sung, Yao-Wen Chang, Shih-Chang Liu