Abstract: In a system and method for managing the operating frequency of processors in a blade-based computer system, a circuit receives a signal with instructions relating to the desired operating frequency of the processors or blades. The circuit then generates a control signal based upon the specific frequency designated by the user. A frequency synthesizer then processes an input frequency signal and the control signal and outputs an output frequency to be used by at least one processor in the blade-based computer system.
Type:
Grant
Filed:
August 12, 2002
Date of Patent:
October 17, 2006
Assignee:
Hewlett-Packard Development Company, L.P.
Inventors:
Ricardo Espinoza-Ibarra, Andrew H. Barr
Abstract: A processor responsive to a clock cycle includes a base-unit, a mirror-unit that is a duplicate instance of the base-unit, a non-duplicate-unit in signal communication with the base and mirror units, a first staging register disposed at the input to the mirror-unit for delaying the input signal thereto by at least one clock cycle, and a second staging register disposed at the output of the mirror-unit for delaying the output signal therefrom by at least one clock cycle. The non-duplicate-unit includes a comparator for comparing the output signals of the base and mirror units.
Type:
Grant
Filed:
May 12, 2003
Date of Patent:
July 25, 2006
Assignee:
International Business Machines Corporation
Inventors:
Michael Billeci, Chung-Lung K. Shum, Timothy J. Slegel