Abstract: A method of memory space allocation, performed within a coherent memory of a computer system, for allocating a line of the memory to a device using an ownership-only command, which transfers ownership of the line of memory without transferring the data contained within the line. After receiving the command, the memory then determines if the line was previously allocated to a second device using a conventional read command, the memory sends a flush command to the second device, and retrieves the contents of the line from the second device. After retrieving the contents of the line, or if the second device used the ownership-only command, the memory sends an ownership acknowledgment for the line to the first device, receives replacement data for the line from the first device, and then releases ownership of the line.

Abstract: A device for processing and storing data, in particular a chip card, includes a first interface with contacts and a second contactless interface for receiving energy or power from and for communication with a terminal device. A first controllable switching device connects either the first or the second interface to a non-volatile semiconductor memory through address, data and control lines. A logic circuit drives the first controllable switching device. A second controllable switching device disposed between the first controllable switching device and the memory can be driven at least by the logic circuit and an address signal present on the address lines.

Abstract: The present invention provides a method and apparatus for storing additional information, such as HOLE information, within a buffer while minimizing the overhead.A method according to the present invention for efficiently storing additional information in a memory, the memory including at least one address, the memory for storing at least a portion of a packet to be transferred by a network system, the method comprising the steps of determining whether the at least a portion of a packet ends at a boundary of the at least one address; encoding a portion of the packet to indicate that the packet ends at the address boundary if the packet ends at the address boundary; and encoding a portion of the at least one address to indicate that the packet does not end at the address boundary, if the packet does not end at the address boundary.

Abstract: A method in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes for servicing a first memory access request by a first node of the computer network pertaining to a memory block having a home node different from the first node in the computer network. The computer network has no natural ordering mechanism and natural broadcast for servicing memory access requests from the plurality of nodes. The home node has no centralized directory for tracking states of the memory block in the plurality of nodes. The method includes the step of receiving via the common network infrastructure at the home node from the first node the first memory access request for the memory block.

Abstract: A technique for controlling memory access ordering in a multi-processing system in which a sequence of accesses to acquire, access and release a shared space of memory is strictly adhered to by use of two specialized instructions for controlling memory access. Two instructions noted as MFDA (Memory Fence Directional--Acquire)and MFDR (Memory Fence Directional--Release) are utilized to control the ordering. The MFDA instruction when encountered in a program operates to ensure that all previous accesses to the specified address (typically to a lock controlling access to the shared space) become visible to other processors before all future accesses are permitted. The MFDR instruction when encountered in a program operates to ensure that all previous accesses become visible to other processors before any future accesses to the specified address.

Abstract: When a synchronization point is determined to maintain the coherence of data in a multi-processor system, and data write-back operations from caches to a main memory are simultaneously performed at the determined point, the traffic is concentrated, resulting in poor efficiency. In view of this problem, the write-back operations of cache data are arbitrarily performed when a predetermined condition is satisfied. Alternatively, when the number of copies which are updated in the cache and do not match the corresponding data in the main memory exceeds a predetermined value, cache data are written back. With this control, the write-back operations of copies stored in cache can be prevented from being concentrated at the synchronization point.

Abstract: A memory access system including a logic/control circuit, a memory, an address bus connecting the logic/control circuit and the memory and an address transition detector circuit provided on address lines constituting the address bus, the address transition detector circuit detecting a memory access signal requesting memory access involving word line switching in the memory out of memory access signals transmitted from the logic/control circuit to the memory through the address lines and outputting a detection signal, and the logic/control circuit receiving input of the detection signal from the address transition detector circuit to temporarily stop its operation until the memory access is completed.

Abstract: A method and apparatus for tracking the fill status of sub cache line locations during a cache line fill operation is provided. The tracking system monitors the data cycles of a burst read during a cache line fill, and sets indicators pertaining to which of the sub cache lines within the cache line have been filled. Cache control utilizes the indicators to make those sub cache lines that have been filled available to a processing system as they are filled, rather than waiting for the entire cache line to be filled. Data is stored directly into sub cache line locations without requiring a cache line buffer.

Abstract: A system and method for improving arbitration of a plurality of events that may require access to a cache is disclosed. In a first aspect, the method and system provide dynamic arbitration. The first aspect comprises first logic for determining whether at least one of the plurality of events requires access to the cache and for outputting at least one signal in response thereto. Second logic coupled to the first logic determines the priority of each of the plurality of events in response to the at least one signal and outputs a second signal specifying the priority of each event. Third logic coupled to the second logic grants access to the cache in response to the second signal. A second aspect of the method and system provides user programmable arbitration. The second aspect comprises a storage unit which allows the user to input information indicating the priority of at least one of the plurality of events and outputs a first signal in response to the information.

Abstract: A method and apparatus for tracking the fill status of subcache line locations during a cache line fill operation is provided. The tracking system monitors the data cycles of a burst read during a cache line fill, and sets indicators pertaining to which of the sub cache lines within the cache line have been filled. Cache control utilizes the indicators to make those sub cache lines that have been filled available to a processing system as they are filled, rather than waiting for the entire cache line to be filled. Data is stored directly into sub cache line locations without requiring a cache line buffer.