Abstract: A vestigial sideband/quadrature amplitude modulation (VSB/QAM) receiver, which receives both VSB and QAM signals and restores a carrier wave with a restored symbol clock after restoring a symbol timing in a front portion of a carrier wave restoration unit.

Abstract: An improvement to system clock synchronization corrector in a digital transceiver allows the generation of a phase error correction signal for use in an imbedded clock synchronization control loop without the use of additional transmitted information or additional external circuitry. The system allows a transceiver to achieve timing and synchronization lock to a system master clock, such as a T1 or E1 clock, by triggering a counter to supply a count responsive to a higher-frequency replica of the local clock signal with the network clock signal. A network timing reference unit generates a phase error offset by clocking data into comparison registers in response to the maximum counter values. Subsequent counter values are mathematically combined to generate a series of phase offset samples. The phase error samples may be stored and or further manipulated to generate a phase error correction signal for use in a clock synchronization control loop.

Abstract: A method for equalizing a signal in a transceiver includes receiving an analog signal and adaptively equalizing the analog signal in an adaptive equalization filter to produce an analog filtered signal. The method also includes converting the analog filtered signal to a digital signal, digitally adapting the digital signal in a digital finite impulse response (FIR) filter, and modifying at least one digital filter coefficient of the digital FIR filter according to a signal error associated with an output of the digital FIR filter. The method further includes providing the at least one modified digital filter coefficient of the digital FIR filter to an analog equalization controller. In addition, the method includes using the at least one modified digital filter coefficient of the digital FIR filter in the analog equalization controller to adaptively equalize the analog signal in the adaptive equalization filter.

Abstract: A system for changing the sample rate of a digital signal precisely such that frequency coherence is maintained. The system uses coupled direct digital synthesizers to establish the phase of a resampled clock compared to the original clock. The system implements precision resampling that changes the sample rate of a sampled data signal, while maintaining the frequency coherence of the sampled signal. A precision phase calculation for the relation between an input clock and an output clock enables the precision resampling.