Abstract: Channel equalization in a 1000BASE-T receiver is performed by a fixed mode analog filter 2 suitable for the longest possible cable length, by a FFE (3), and by a digital filter 4. The digital filter (4) has two sets of taps. One set is optimal for shorter cable lengths and so cancels adaptation for long cable lengths and assists operation of the analog filter. A decision block (5) selects an appropriate set of taps.

Abstract: Processing of a received code division multiple access, CDMA, burst (405) when a spreading factor of the CDMA burst (405) has been changed from an allocated spreading factor (SF0) to a new spreading factor (SFn). The received burst (405) is processed with a CDMA detector (310), using the allocated spreading factor (SF0), to provide a CDMA detector output; the new spreading factor (SFn) of the burst is determined; and the CDMA detector output is decimated by a factor determined from the new spreading factor (SFn). The decimator may be a FIR decimator (315) and tap weights may be determined using the values of the new spreading factor (SFn) and the allocated spreading factor (SF0). Application in a Node B (150A) of a UMTS system (100), particularly in UTRA TDD mode, for processing received uplink communication is described.

Abstract: Estimation of gain and phase imbalance of an upconverting transmitter. A transmitter transmits symbols containing vector components of pre-specific relationship in an analog signal. A receiver (also contained in a transceiver along with the transmitter) examines the symbols to determine the phase and gain imbalances in the transmitter based on the analog signal. An aspect of the present invention enables the balance estimation circuit to be integrated along with the transmitter and the receiver into a single monolithic integrated circuit.

Abstract: A receiver for iterative decoding of a received, encoded signal employs slot-based scaling of soft samples. Iterative decoding employs a constituent maximum a priori (MAP) decoder for each constituent encoding of information of the encoded signal. Root mean square (RMS) values for soft samples over a slot are selected for dynamic range scaling. Squared RMS values are combined and equal the squared RMS value for a frame multiplied by a control constant, and this relationship may be employed to derive scaling constants for each slot. Alternatively, the square root of the RMS value multiplied by a constant serves as an SNR estimator that may be employed to scale samples to reduce dynamic range and modify logarithmic correction values for max* term calculation during log-MAP decoding.

Abstract: The invention relates to a method for synchronizing a plurality of digital input signals which are formed by sampling with the aid of a dedicated operating clock in each case. In order to be able to carry out such a method reliably with a relatively low outlay, according to the invention digital auxiliary signals (xd(nk+j), (yd(nk+j)) are formed by sampling the digital input signals (x(k)) with the aid of a common postprocessing clock, use being made of a postprocessing clock which is at least twice as fast as the fastest operating clock; synchronized digital output signals (x(m), y(m)) which correspond to the digital input signals (x(k)) are formed by means of interpolating each digital auxiliary signal (xd(nk+j), yd(nk+j)).

Abstract: In an amplifier system that linearizes an amplifier by pre-distorting the input signal prior to amplification, a baseband pre-distortion processor processes the input signal in a digital baseband domain to generate one or more pre-distortion parameters based on the power of the digital baseband input signal. The digital baseband signal is up-converted and D/A-converted into a non-baseband (e.g., IF or RF) signal which is then pre-distorted, e.g., using a phase/gain adjuster or a vector modulator. By generating the pre-distortion parameters at baseband, while pre-distorting the input signal at non-baseband, the amplifier system avoids the cost and inaccuracies associated with analog signal delay and RF power detection of prior-art “all-RF” pre-distortion implementations, while avoiding the wider-bandwidth filtering of prior-art “all-baseband” pre-distortion implementations.

Abstract: An orthogonal code generation apparatus can generate a sequence of orthogonal codes without having to prestore orthogonal code sequences in a memory, by applying logic operation on a sequence number and a location number using AND circuits A0, A1, A2, A3, . . . , An and an adder circuit. A scrambling code generation apparatus computes only the values of registers involved with a feedback operation and a spreading operation, and loads respective values into the registers while shifting the shift register. When all the registers store valid values, scrambling codes are generated by a shift operation of the shift register.

Abstract: In the channel quality information (CQI) coding method of the present invention, first basis sequences for generating sub-codes of 32 bits are created, and second basis sequences for generating codewords of 20 bits are created using the first basis sequences, the second basis sequence maximizing system throughput such that five information bits are coded into CQI code using the second basis sequences. Also, since HSDPA system has been designed in order to increase the system throughput, the CQI coding method of the present invention, which shows the best system throughput in the simulation, can be the optimum CQI coding scheme for HS-DPCCH.

Abstract: The present invention provides asymmetric digital subscriber line (ADSL) modems including a discrete multitone (DMT) modem module. The DMT modem module includes a digital signal processor (DSP) configured to process control signals for initializing the ADSL modem during installation associated with a host device and transmit the processed control signals to a host controller of the host device.

Abstract: A transceiver for communicating a multi-tone modulated communication channel on a subscriber line. The transceiver includes: a digital signal processor (DSP) with a Fourier transform module and an analog front end (AFE). The DSP determines an available range of frequencies on the subscriber line and expands or contracts the tone spacing of each of a fixed number “N” of tones accordingly by decreasing or increasing the processing interval associated with the Fourier transform of each tone set. The AFE performs digital-to-analog conversion of the multi-tone modulated communication channel at rates compatible with the processing interval of the Fourier transform module; whereby the range of frequencies spanned by the modulated tones on the subscriber line conforms to the available of frequencies on the subscriber line.

Abstract: Methods, apparatus and systems for implementing an algorithm for N-symbol noncoherent processing of M-ary DPSK signals in a pilotless, wireless system is provided. The algorithm is carried out with (N?1) recurrent steps (iterations) plus a decision step. Each iterative step includes simple trigonometrical transformation of quadrature components of the current symbol and summation of the transforms with results of the previous step. A final N-symbol decision regarding the current transmitted symbol corresponds to the vector of maximum length, calculated after the (N?1)-th step of the iterative procedure. The general algorithm is optionally implemented with one or more intersymbol processors, one or more memory blocks for saving results of the intersymbol processors, and a decision block. In addition, shift registers for quadrature components of the received signal may be utilized.

Abstract: In a digital broadcast receiving apparatus for amplifying a received modulated digital signal wave with automatically adjusted gain and demodulating the modulated signal wave to a digital signal, a tuner frequency-converts the modulated digital signal wave to generate a first modulated signal. A first automatic gain control amplification unit controls gain of the tuner to make a level of the first modulated signal at a first predetermined level. An A/D converter converts the first modulated signal into a second modulated signal. A demodulator demodulates the second modulated signal to generate a first demodulated digital signal. A second automatic gain control amplifier generates a second demodulated digital signal where frequency fluctuations included in the digital modulated wave are eliminated.

Abstract: A vestigial sideband (VSB) modulation transmission system and a method for encoding an input signal in the system are disclosed. According to the present invention, the VSB transmission system includes a convolutional encoder for encoding an input signal, a trellis-coded modulation (TCM) encoder for encoding the convolutionally encoded signal, and a signal mapper mapping the trellis-coded signal to generate a corresponding output signal. Different types of the convolutional encoders are explored, and the experimental results showing the performances of the VSB systems incorporating each type of encoders reveals that a reliable data transmission can be achieved even at a lower input signal to noise ratio when a convolutional encoder is used as an error-correcting encoder in a VSB system.

Abstract: A stereo demultiplexer is proposed which can be calculation power efficiently implemented in a DSP. Modern digital FM receivers exploit the information content in the in quadrature component of the modulated difference signal for a noise reduction. The proposed stereo demultiplexer derives the in phase component and the in quadrature component of the difference signal with a minimized number of sinus and cosinus calculations by first downconverting the modulated difference signal to a not synchronized complex baseband signal on basis of a fixed frequency, thereafter a complex sampling rate decimation unit sampling rate decimates the not synchronized complex baseband signal with a factor N and a second complex mixer synchronizes and coherent demodulates the sampling rate decimated not synchronized baseband signal on basis of a first complex carrier signal derived on basis of the pilot carrier signal and the fixed frequency.

Abstract: A system and method for arbitrating among frequency-hopping spread spectrum communication systems are provided herein. An arbitrator calculates and compares hop frequencies for the communication systems of an area or network using frequency generation parameters received from the communication systems. The comparison identifies impending transmission collisions and collision frequencies for transmission time slots. The arbitrator then selects one of the radios associated with an impending collision to transmit, and suppresses or disables transmissions by non-selected radios during the same transmission time period for that frequency. Thus, the arbitrator minimizes bandwidth lost to co-channel and adjacent channel collisions by reducing or eliminating this mutual interference among the communication systems.

Abstract: A method of and apparatus for single antenna interference rejection (SAIR) relaxation. Interference in a received signal is reduced by performing synchronization and whitening of the received signal. The synchronization and whitening includes performing the following steps at least one time: 1) performing a synchronization and vector-noise-correlation estimation of an input signal to yield an interference model; and 2) performing a spatio-temporal whitening operation using the interference model and the input signal to yield an updated received signal. The input signal is the received signal when the step of performing the synchronization and vector-noise-correlation estimation is performed a first time. The input signal is the updated received signal when the step of performing the synchronization and vector-noise-correlation estimation is performed following the first time.

Abstract: A synchronizing position detecting circuit includes a window size determining circuit, a synchronizing code generating circuit, a correlation circuit and a synchronizing position determining circuit. The window size determining circuit calculates a moved distance of a mobile station during a sleep time based on a moving speed and the sleep time and selects a window size based on a phase change of a distance signal corresponding to the moved distance. The code generating circuit repeatedly produces a synchronizing code that coincides with a part of a code of the distance signal and successively shifts a phase of the synchronizing code by a predetermined phase width so as to shift the window size. The correlation circuit calculates a correlation function between the synchronizing code and the distance signal. The position determining circuit determines a correlation function having a maximum value to detect the distance signal and outputs a synchronizing position signal representing a detecting position.

Abstract: Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.

Abstract: According to some embodiments, distances associated with a Trellis decoder are determined.

Abstract: Method and apparatus for data recapture from a source synchronous interface. A data signal is obtained via the source synchronous interface. A timing signal is obtained via the source synchronous interface, where the data signal and the timing signal are provided in association with one another. The timing signal is frequency divided by frequency divider to provide an enable signal. Data of the data signal is captured responsive to the timing signal and the enable signal, where the data captured is in a time domain of the timing signal. A data valid signal is generated from the enable signal and an internal clock signal, where the data valid signal is internally timed without having to determine a system level delay. The data is recaptured responsive to the internal clock signal and the data valid signal, where the recaptured data is in a time domain of the internal clock signal.