Abstract: A semiconductor device has memory cells, a bias circuit and a charging circuit. A conductive or non-conductive state of the memory cells is read out by the bias circuit and the charging circuit as data in the memory cells. The device also includes a control circuit having a supply voltage detection circuit in which a first N-channel depletion-mode MOSFET whose drain and gate electrodes are connected in common, and a second N-channel depletion-mode MOSFET whose source and gate electrodes are connected in common, are connected in series between the power supply terminal and the ground potential terminal. The series junction node formed between the first and second MOSFETs is connected to one input terminal of a NOR gate while an inverted signal line for a semiconductor device enabling signal is connected to the other input terminal, and an output terminal of the NOR gate is connected to an input terminal of an inverter, an output of the inverter being used as a control signal for enabling the charging circuit.