Abstract: The dual port DRAM comprises a SAM section having a plurality of registers, for inputting and outputting data in series between a SAM input/output port and the outside in synchronism with a control signal; a RAM section having a plurality of memory cells, for inputting and outputting data at random between a RAM input/output port and the outside; a plurality of transfer gates connected between the SAM section and the RAM section, for transferring data in parallel; and a selecting section for selectively turning on or off only the transfer gates connected to the registers in the SAM section to which data are inputted from the SAM input/output port in series in synchronism with the control signal, to execute partial parallel-data transfer from the SAM section to the RAM section via the transfer gates.