Patents Examined by F. Niransam
  • Patent number: 5596529
    Abstract: A select MOS transistor and a data storage MOS transistor are formed in an element region. The transistor has floating-gate electrodes. The floating-gate electrodes are spaced apart above the element region and connected to each other above a field region. Only a tunnel insulating film much thinner than a gate insulating film of the transistor is placed between the floating-gate electrode and a drain region. Only the gate insulating film much thinner than the gate insulating film of the transistor is placed between the floating-gate electrode and the channel region of the transistor. In the element region, the shape of a control electrode is the same as that of the floating-gate electrodes.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: January 21, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichiro Noda, Daisuke Tohyama