Abstract: A single chip semiconductor integrated circuit device having a central processing unit (CPU) and a flash memory which stores data to be processed by the CPU and which provides data to the CPU through the data bus in response to accessing instructions from the CPU through the address bus. The flash memory is constituted by a plurality of memory arrays in which a plurality of word lines are commonly employed for all of the memory arrays and a plurality of data lines are distributed amongst the memory arrays. The nonvolatile memory cells are arranged in a manner in which plural memory blocks are formed. The memory blocks formed can be facilitated with different memory capacities. This is achieved by having one or more rows of memory cells associated with one or more word lines provided within a memory block.

Abstract: A semiconductor memory device includes a series circuit composed of a drive MOS transistor as a first MOS transistor and a reset MOS transistor as a second MOS transistor connected in series via a common connection node, a source of the reset MOS transistor being connected to a lower potential power supply, a main word line, and a sub-word line connected to the common connection node. An address signal includes a first part and a second part and a row address signal section decodes the first part of the address signal to generate a first row address signal and a second row address signal having a phase inverse to that of the first row address signal in accordance with the decoding result, and supplies the first row address signal to a drain of the drive MOS transistor and the second row address signal to a gate of a reset MOS transistor.

Abstract: A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.

Abstract: A semiconductor device has a precharge control circuit for generating a precharge control signal, the precharge control signal being at an active level when all word lines do not indicate a high level and being at an inactive level when an access control signal (read control signal or write control signal) is input to the precharge control circuit for controlling a precharge circuit for precharging bit lines to a predetermined voltage.

Abstract: A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.

Abstract: A DRAM with improved stacked-capacitor memory cells is provided. In each memory cell, an aluminum wiring line acting as a part of one of word lines is covered with a interlayer insulator film, and on the interlayer insulator film, a storage capacitor is formed. A storage electrode of the capacitor is contacted with a source/drain region of an MOS select transistor through a contact hole in the interlayer insulator film. The wiring line is not required to be formed over the capacitor and as a result, thickness of the storage electrode of the capacitor is not limited by a fabrication condition. Thus, a dielectric such as Ta.sub.2 O.sub.5 with a larger dielectric constant can be employed as the capacitor dielectric, so that the memory cell area can be reduced.