Abstract: In a method of treating a target film, a plurality of pattern structures with sidewall surfaces facing each other are provided. A target film is formed on the sidewalls of the plurality of pattern structures. A plurality of nanoparticles are distributed on the target thin film. The target thin film is thermally treated by irradiating laser light from upper sides of the plurality of pattern structures to the target thin film. The irradiated laser light is scattered from the plurality of nanoparticles.

Abstract: Method of doping a semiconductor sample in a uniform and carbon-free way, wherein said sample has a surface, comprising the following steps: A. removing oxides from at least part of the said surface; B. dip coating said at least part of the surface of the sample in a dopant based carbon-free solution of at least one dopant based carbon free substance diluted in water, wherein said at least one dopant based carbon free substance has a molecule comprising at least one dopant atom, wherein the dip coating is achieved by heating said dopant based carbon-free solution at a dip coating temperature from 65% to 100% of the boiling temperature of said dopant based carbon-free solution, thereby a self-assembled mono-layer including dopant atoms is formed; C. annealing said sample, wherein the annealing is configured to cause said dopant atoms included in said self-assembled mono-layer to be diffused into the sample.

Abstract: A method for processing a substrate includes performing a cyclic plasma process including a plurality of cycles, each cycle of the plurality of cycles including purging a plasma processing chamber including the substrate with a first deposition gas including carbon. The substrate includes a first layer including silicon and a second layer including a metal oxide. The method further includes exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymeric film over the first layer relative to the second layer; purging the plasma processing chamber with an etch gas including fluorine; and exposing the substrate to a second plasma generated from the etch gas to etch the second layer.

Abstract: A vapor phase epitaxy method of growing a III-V layer with a doping profile that changes from a p-doping to an n-doping on a surface of a substrate or a preceding layer from the vapor phase from an epitaxial gas flow, at least one first precursor for an element of main group III, and at least one second precursor for an element of main group V. When a first growth height is reached, a first initial doping level is set by means of a ratio of a first mass flow of the first precursor to a second mass flow of the second precursor in the epitaxial gas flow, and subsequently, by stepwise or continuously changing the ratio of the first mass flow to the second mass flow and by stepwise or continuously increasing a mass flow of a third precursor for an n-type dopant in the epitaxial gas flow.

Abstract: A process to form a HEMT can have a gate electrode layer that initially has a plurality of spaced-apart doped regions. In an embodiment, any of the spaced-apart doped regions can be formed by depositing or implanting p-type dopant atoms. After patterning, the gate electrode can include an n-type doped region over the p-type doped region. In another embodiment a barrier layer can underlie the gate electrode and include a lower film with a higher Al content and thinner than an upper film. In a further embodiment, a silicon nitride layer can be formed over the gate electrode layer and can help to provide Si atoms for the n-type doped region and increase a Mg:H ratio within the gate electrode. The HEMT can have good turn-on characteristics, low gate leakage when in the on-state, and better time-dependent breakdown as compared to a conventional HEMT.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.

Abstract: A patterning method includes at least the following steps. A first material layer is provided. A second material layer is provided over the first material layer. The second material layer partially exposes the first material layer. A passivation layer is formed over the first material layer and the second material layer. A growth rate of the passivation layer on the second material layer is greater than a growth rate of the passivation layer on the first material layer. A first etching process is performed to remove a portion of the passivation layer and a portion of the first material layer.

Abstract: A semiconductor device that includes a semiconductor substrate; a first capacitance section on the semiconductor substrate, the first capacitance section including a first electrode layer, a first dielectric layer, and a second electrode layer; a second capacitance section on the semiconductor substrate, the second capacitance section including a third electrode layer, a second dielectric layer, and a fourth electrode layer; a first external electrode; a second external electrode; a first lead wire led out from the first capacitance section to the first external electrode and having an inductance L1; and a second lead wire led out from the second capacitance section to the second external electrode and having an inductance L2, wherein an electrostatic capacity C1 of the first capacitance section and an electrostatic capacity C2 of the second capacitance section are different, and L1/L2=0.8 to 1.2.

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.

Abstract: A field effect transistor comprising: a first semiconductor structure, the first semiconductor structure having a channel layer; a second semiconductor structure, the second semiconductor structure is arranged on the first semiconductor structure, and the second semiconductor structure is stacked in sequence from bottom to top with a Schottky layer, a first etch stop layer, a wide recess layer, an ohmic contact layer, and a narrow recess, a wide recess is opened in the ohmic contact layer, so that the upper surface of the wide recess layer forms a wide recess area and the upper surface of the Schottky layer forms a narrow recess area; at least one delta-doped layer, a gate metal contact, the gate metal contact is formed inside the wide recess a source metal contact; and a drain metal contact, and the drain metal contact is located on the other side of the gate metal contact.

Abstract: A vapor phase epitaxy method of growing a III-V layer with a doping that changes from a first conductivity type to a second conductivity type on a surface of a substrate or a preceding layer in a reaction chamber from the vapor phase from an epitaxial gas flow comprising a carrier gas, at least one first precursor for an element from main group III, and at least one second precursor for an element from main group V, wherein when a first growth height is reached, a first initial doping level of the first conductivity type is set by means of a ratio of a first mass flow of the first precursor to a second mass flow of the second precursor in the epitaxial gas flow, the first initial doping level is then reduced to a second initial doping level of the first or low second conductivity type.

Abstract: Provided are a thermal sensor and a manufacturing method thereof. The thermal sensor includes a transistor and a thermal sensing device. The thermal sensing device is disposed in a recess in a substrate and electrically connected to the transistor. The thermal sensing device includes a first dielectric layer, a metal silicide reflective layer, a second dielectric layer, and a thermal absorbing layer. The first dielectric layer is disposed on sidewalls and a bottom of the recess. The metal silicide reflective layer is disposed on the first dielectric layer located on the bottom of the recess. The second dielectric layer is disposed at a top of the recess. The thermal absorbing layer is disposed on the second dielectric layer.

Abstract: A memory cell structure including a dielectric cap layer disposed over a substrate and a first dielectric layer disposed over the dielectric cap layer. The memory cell structure may further include a buffer layer disposed over the first dielectric layer, a connection via structure embedded in the buffer layer, the first dielectric layer, and the dielectric cap layer. The memory cell structure may further include may further include a bottom electrode disposed on the connection via structure and the buffer layer, and a magnetic tunnel junction (MTJ) memory cell including one or more MTJ layers disposed on the bottom electrode.

Abstract: A disclosed etching method includes (a) etching a titanium nitride film with a first plasma, and (b) etching the titanium nitride film with a second plasma. The first plasma is generated from a first processing gas, and the second plasma is generated from a second processing gas. One of the first processing gas and the second processing gas contains a chlorine-containing gas and a fluorocarbon gas, and the other of the first processing gas and the second processing gas contains a chlorine-containing gas and does not contain a fluorocarbon gas. A repetition of a cycle including the operations (a) and (b) is performed. The repetition of the cycle is stopped in a state where the titanium nitride film is partially etched in a film thickness direction thereof.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure having an electrical contact. The method includes providing a semiconductor substrate; forming a dielectric structure over the semiconductor substrate, the dielectric structure having a trench; filling a polysilicon material in the trench of the dielectric structure; detecting the polysilicon material to determine a region of the polysilicon material having one or more defects formed therein; implanting the polysilicon material with a dopant material into the region; and annealing the polysilicon material to form a doped polysilicon contact.

Abstract: A manufacturing method of a memory device includes the following steps. Memory units are formed on a substrate. Each of the memory units includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a sidewall portion of the non-conformal spacer layer and a sidewall portion of the conformal spacer layer in the vertical direction.

Abstract: A semiconductor device includes a peripheral circuit region with a first substrate, circuit devices on the first substrate, and a first wiring structure, a memory cell region with a second substrate that has a first region and a second region, gate electrodes stacked in the first region, channel structures that penetrate the gate electrodes, a first horizontal conductive layer on the second substrate in the first region, an insulating region on the second substrate in the second region, a second horizontal conductive layer on the first horizontal conductive layer and the insulating region, and a second wiring structure, and a third wiring structure that connects the first substrate to the second substrate, and includes an upper via that penetrates the second horizontal conductive layer, the insulating region, and the second substrate, and a lower wiring structure connected to the upper.

Abstract: A method for manufacturing a gallium nitride semiconductor device includes: preparing a gallium nitride wafer; forming an epitaxial growth film on the gallium nitride wafer to provide a processed wafer having chip formation regions; perform a surface side process on a one surface side of the processed wafer; removing the gallium nitride wafer and dividing the processed wafer into a chip formation wafer and a recycle wafer; and forming an other surface side element component on an other surface side of the chip formation wafer.

Abstract: Embodiments of the invention relate to a method for fabricating a semiconductor structure comprising a semiconductor material, and a semiconductor substrate fabricated from the method. The method can include a step of providing a template structure. The template structure can comprise an opening, a cavity and a seed structure. The seed structure can comprise a seed material and a seed surface. An inner surface of the template structure can comprise at least one metallic surface area comprising a metallic material. The embodied method further comprises a step of growing the semiconductor structure within the cavity of the template structure from the seed surface along the metallic surface area.

Abstract: A method for etching a hardmask layer includes forming a photoresist layer comprising an organometallic material on a hardmask layer comprising a metal-containing material, exposing the photoresist layer to ultraviolet radiation through a mask having a selected pattern, removing un-irradiated areas of the photoresist layer to pattern the photoresist layer, forming a passivation layer comprising a carbon-containing material selectively on a top surface of the patterned photoresist layer, and etching the hardmask layer exposed by the patterned photoresist layer having the passivation layer formed thereon.