Patents Examined by Felisa Garrett
  • Patent number: 5735951
    Abstract: A single crystal pulling apparatus which eliminates trouble caused by an isolation valve heated to a high temperature uses a heat insulation plate provided below the isolation valve. The heat insulation plate is operated synchronously with the opening or closing of the isolation valve. The heat insulation plate prevents hot gases from coming from the lower chamber from coming into direct contact with the isolation valve. The prevention of overheating of the isolation valve provides for smooth operation and growth of a good quality single crystal.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: April 7, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Eiichi Iino, Kiyotaka Takano, Masanori Kimura, Koji Mizuishi, Hirotoshi Yamagishi
  • Patent number: 5733368
    Abstract: In a method of manufacturing a silicon monocrystal using a continuous Czochralski method, a silicon monocrystal is pulled from a silicon melt in a crucible while a silicon material is fed to the crucible. Supply of the silicon material is suspended until the temperature distribution of the silicon melt becomes stable after initiation of a straight body forming process, and the supply of the silicon material is commenced when the temperature distribution of the silicon melt has become stable. The feed rate of the silicon material is gradually increased until the feed rate becomes equal to a solidification rate of the silicon melt after the supply of the silicon material has been commenced. This method prevents the silicon monocrystal from becoming a polycrystal during the manufacture thereof.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: March 31, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Naoki Nagai, Isamu Harada, Michiaki Oda
  • Patent number: 5730798
    Abstract: A method of masking semiconductor substrates during fabrication of semiconductor devices includes positioning an oxide mask on the substrate so as to define a growth area and an unmasked portion the surface. A dense oxide layer is grown on the unmasked portion and the oxide mask is removed to expose the growth area. The substrate is introduced into a growth chamber and heated to approximately 580.degree.-600.degree. C. to desorb any native oxide in the exposed growth area. Crystalline material is selectively grown on the exposed growth area and the substrate is heated to approximately 640.degree. C. under high arsenic flux to desorb the dense oxide layer, without removing the substrate from the chamber.
    Type: Grant
    Filed: August 7, 1995
    Date of Patent: March 24, 1998
    Assignee: Motorola
    Inventor: Kumar Shiralagi
  • Patent number: 5730800
    Abstract: An improved method is proposed for the preparation of a semiconductor silicon single crystal of N-type by the Czochralski process, which is free from the problem of occurrence of delayed OSFs as defects in the single crystal even after prolonged storage at room temperature based on the discovery that presence of a certain amount of aluminum in the melt of silicon contained in a fused silica glass crucible acts to suppress occurrence of delayed OSFs as a type of defects in the single crystal while copper as an impurity acts adversely in this regard. With a known fact that an about 30 .mu.m thick inner surface layer of the crucible is melted down into the silicon melt during the single crystal pulling-up process, namely, the invention proposes use of a crucible of which the inner surface layer of 30 .mu.m thickness contains aluminum in an average concentration of 40 to 500 ppm by weight while the content of copper is as low as possible not to exceed 0.5 ppb by weight.
    Type: Grant
    Filed: December 17, 1996
    Date of Patent: March 24, 1998
    Assignees: Shin-Etsu Handotai Co., Ltd., Shin-Etsu Quartz Products Co., Ltd.
    Inventors: Wataru Sato, Masahiro Sakurada, Ohta Tomohiko, Katsuhiko Kemmochi
  • Patent number: 5730799
    Abstract: A device for producing single crystals has been presented which enables the pulling up and growing of single crystals. Without loss of accurate control of the oxygen concentration in the crystal, and with excellent dielectric strength of subsequently produced gate oxide films. A heat resistant and heat insulating component (7) of cylindrical or cylinder-like form surrounding the pulling up zone of the single crystal is suspended from the ceiling (6a) or the upper part of the wall of the metallic vessel (6) with a gap (h.sub.1) from the ceiling to divide the inert gas (30) supplied from above into inert gas flows (33 and 32) outside and inside this component.
    Type: Grant
    Filed: November 27, 1995
    Date of Patent: March 24, 1998
    Assignee: Sumitomo Sitix Corporation
    Inventor: Makoto Ito
  • Patent number: 5728214
    Abstract: When a cuprate oxide LnBa.sub.2 Cu.sub.3 O.sub.7-x (Ln=Y, Pr or Sm; 0.30.ltoreq.x.ltoreq.1) single crystal is heated for growing a film epitaxially on the crystal or for smoothing a damaged surface of the single crystal, many large protrusions occur on the surface of the oxide single crystal substrate or the film. The smooth surface of the oxides becomes rugged by the protrusions. According to the present invention, however, the oxide substrate or the oxide superconductor film can be heated in an atmosphere including oxygen of a partial pressure between 50 mTorr and 200 mTorr to prevent the protrusions from originating on the surface of the heated oxides.
    Type: Grant
    Filed: September 6, 1995
    Date of Patent: March 17, 1998
    Assignees: Sumitomo Electric Industries, Ltd., Kabushiki Kaisha Toshiba, International Superconductivity Technology Center
    Inventors: Masaya Konishi, Hiroyuki Fuke, Youichi Enomoto, Yuh Shiohara, Shoji Tanaka
  • Patent number: 5728213
    Abstract: A method of growing a rare earth silicate single crystal from a melt of a starting material containing a rare earth oxide and a silicon oxide, wherein the starting material in which a density of Fe as an impurity is not more 0.1 ppm, a density of Al as an impurity is not more than 0.4 ppm, or the starting material showing a weight loss of not more than 1.0% when heated up to 1,000.degree. C. is used.This method which makes it possible to stably obtain a rare earth silicate single crystal having a good scintillator performance, such as free of voids and/or non-colored crystals, or may cause no poor fluorescent characteristics due to a compositional deviation of materials.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: March 17, 1998
    Assignee: Hitachi Chemical Company Ltd.
    Inventors: Yasushi Kurata, Hiroyuki Ishibashi, Kazuhisa Kurashige
  • Patent number: 5728212
    Abstract: A compound semiconductor crystal has a reduced dislocation density. The compound semiconductor crystal doped with an impurity satisfies the following relations, wherein c.c. represents its carrier concentration and .eta. represents its activation factor:.eta..ltoreq.c.c./(7.8.times.10.sup.15) (1).eta..ltoreq.(10/19).times.(197-2.54.times.10.sup.-17 .times.c.c.) (2).eta..gtoreq.c.c./(3.6.times.10.sup.16) (3)A method which can prepare a compound semiconductor crystal doped with an impurity and having a prescribed carrier concentration with excellent reproducibility comprises the steps of melting a raw material for the compound semiconductor crystal in a crucible, and controlledly cooling the obtained raw material melt, thereby growing a crystal. The time required for cooling the raw material melt from the melting point T of the raw material to 2/3T is so controlled as to adjust the carrier concentration to a prescribed level.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: March 17, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tetsuya Inoue, Yoshiaki Hagi
  • Patent number: 5728215
    Abstract: A method for forming a film by selective area growth by MDCVD technique includes forming a mask on a semiconductor substrate having a (100) plane, the mask having a mask opening to selectively growing a compound semiconductor layer, and a slit which is narrower than the mask opening in width and controls the growth rate of the compound semiconductor layer at the mask opening; and selectively growing the compound semiconductor layer at a growth rate which is on the mask in the mask opening and the slit.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: March 17, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takushi Itagaki, Masayoshi Takemi, Norio Hayafuji
  • Patent number: 5728211
    Abstract: A silicon single crystal having low defects, such as flow pattern defects and laser scattering tomography defects, and high dielectric breakdown strength in oxides and a method of producing the same using the Czochralski technique comprising steps of adjusting a first passage time of a growing crystal for a first temperature range of the melting point to 1,200.degree. C. so as to be 190 min. or shorter and adjusting a second passage time thereof for a second temperature range of 1,150.degree. C. to 1,080.degree. C. so as to be 60 min. or longer during crystal growth.
    Type: Grant
    Filed: June 3, 1996
    Date of Patent: March 17, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kiyotaka Takano, Kouji Kitagawa, Eiichi Iino, Masanori Kimura, Hirotoshi Yamagishi, Masahiro Sakurada
  • Patent number: 5728222
    Abstract: An apparatus in a chemical vapor deposition (CVD) system monitors the actual wafer/substrate temperature during the deposition process. The apparatus makes possible the production of high quality aluminum oxide films with real-time wafer/substrate control. An infrared (IR) temperature monitoring device is used to control the actual wafer temperature to the process temperature setpoint. This eliminates all atmospheric temperature probing. The need for test runs and monitor wafers as well as the resources required to perform the operations is eliminated and operating cost are reduced. High quality, uniform films of aluminum oxide can be deposited on a silicon substrates with no need for additional photolithographic steps to simulate conformality that are present in a sputtered (PVD) type application. The result is a reduction in required process steps with subsequent anticipated savings in equipment, cycle time, chemicals, reduce handling, and increased yield of devices on the substrate.
    Type: Grant
    Filed: October 12, 1995
    Date of Patent: March 17, 1998
    Assignee: International Business Machines Corporation
    Inventors: Steven George Barbee, Richard Anthony Conti, Alexander Kostenko, Narayana V. Sarma, Donald Leslie Wilson, Justin Wai-Chow Wong, Steven Paul Zuhoski
  • Patent number: 5725661
    Abstract: An equipment for producing silicon single crystals based on an MCZ method, which enables an operator to be protected from dangerous exposure to magnetic field without involving increase in the size of the silicon single crystal production equipment. In the silicon single crystal production equipment based on the MCZ method, a growth furnace control apparatus for control of a pulling apparatus is located away from the pulling apparatus by a predetermined distance so that the intensity of magnetic field immediately close to the growth furnace control apparatus can become 300 gausses or less. A monitoring camera for observing the growing condition of the silicon single crystal is mounted to a window 5a of a growth furnace to be operatively connected to a monitor of the growth furnace control apparatus and to cause the growth furnace control apparatus to control the pulling apparatus on a remote control basis.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: March 10, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Izumi Fusegawa, Toshiro Hayashi, Tomohiko Ohta, Masayuki Arai
  • Patent number: 5725660
    Abstract: A semiconductor single crystal growing apparatus is vertically and telescopically provided with a seed holder. The seed holder comprises a seed-holding member for holding a seed and a suspending bolt for bolting the seed-holding member. The front end of the seed coincides with a datum point when the seed holder is moved to a top dead point.
    Type: Grant
    Filed: November 29, 1996
    Date of Patent: March 10, 1998
    Assignee: Komatsu Electronic Metals Co. Ltd.
    Inventor: Yoshinobu Hiraishi
  • Patent number: 5725658
    Abstract: When a film is formed on a wafer of groups III-V compound semiconductors by heating, slips are formed in the periphery of the wafer because of residual inner stress of the wafer. The quality of an epitaxially grown crystal is damaged by these slips. The residual stress of the wafer is caused by the residual stress generated in an inner part of an ingot at the time of growing a crystal. Therefore, it is an object to prepare a wafer in which no slips are generated when the epitaxial growth is carried out. In order to achieve this object, a method is provided in which; an ingot is heated and cooled in a range between an upper limit temperature T.sub.h, and a lower limit temperature T.sub.1 where the upper limit temperature ranges from more than 800.degree. C. to less than a melting point of a material of the ingot, and the lower limit temperature ranges from more than 800.degree. C. to less than the upper limit temperature T.sub.h.
    Type: Grant
    Filed: April 6, 1995
    Date of Patent: March 10, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Shin-ichi Sawada
  • Patent number: 5720810
    Abstract: A system for growing high-quality, low-carbon-concentration single crystals which have an excellent gas-flow guiding function near the melt, containing 1) an inverted conical, flow-guide cover placed above and coaxially with a double-walled crucible, with its lower end located immediately above the surface of the melt and in the space between the outer surface of the single crystal to be grown and the inner surface of the sidewall of the inner crucible; 2) a short passage comprising a hole passing through the sidewall of the inner crucible at a position higher than the level of the melt; and 3) a flow guide cylinder placed above and coaxially with the double-walled crucible, with its lower end located immediately above the surface of the melt and in the space between the outer surface of the sidewall of the inner crucible and the inner surface of the sidewall of the outer crucible, all arranged in a furnace.
    Type: Grant
    Filed: August 22, 1995
    Date of Patent: February 24, 1998
    Assignees: Mitsubishi Materials Corporation, Mitsubishi Materials Silicon Corporation
    Inventors: Yoshiaki Arai, Keisei Abe, Norihisa Machida
  • Patent number: 5718762
    Abstract: A method for vapor-phase growth which allows an epiwafer of a smooth surface free from microroughness to be produced is provided. This method comprises a step of heating up a silicon single crystal substrate in an ambience of an inert gas started at a temperature of less than 800.degree. C. and a step of removing a native oxide film formed on the surface of the silicon single crystal substrate by etching with hydrogen gas in an ambience of hydrogen gas at a temperature of not less than 950.degree. C. and not more than 1190.degree. C. prior to the vapor-phase growth.
    Type: Grant
    Filed: February 27, 1996
    Date of Patent: February 17, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hitoshi Habuka, Naoto Tate, Masanori Mayuzumi, Hitoshi Tsunoda, Masatake Katayama
  • Patent number: 5718760
    Abstract: Large single crystals of silicon carbide are grown in a furnace sublimation system. The crystals are grown with compensating levels of p-type and n-type dopants (i.e., roughly equal to levels of the two dopants) in order to produce a crystal that is essentially colorless. The crystal may be cut and fashioned into synthetic gemstones having extraordinary toughness and hardness, and a brilliance meeting or exceeding that of diamond.
    Type: Grant
    Filed: February 5, 1996
    Date of Patent: February 17, 1998
    Assignee: Cree Research, Inc.
    Inventors: Calvin H. Carter, Valeri F. Tsvetkov, Robert C. Glass
  • Patent number: 5714004
    Abstract: For the highly repeatable growth of high-quality semiconductor polycrystals with excellent crystallographic properties, at a low cost, there are provided a process for producing a polycrystalline semiconductor including charging a raw semiconductor material into a crucible with semiconductor seed crystals placed on its bottom in an atmosphere inert to the semiconductor, heating to melt the raw semiconductor material in the crucible by heating means while depriving the bottom of the crucible of heat to maintain the underside temperature T1 of the bottom below the melting point of the raw semiconductor material, and then cooling the crucible to solidify the melted material, wherein the underside temperature T1 of the bottom of the crucible under heating is measured, and the heating by the heating means is suspended when the rate .DELTA.
    Type: Grant
    Filed: May 13, 1996
    Date of Patent: February 3, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tetsuhiro Okuno
  • Patent number: 5714008
    Abstract: Apparati and methods for varying the flux of a molecular beam emanating from an effusion cell are disclosed. The apparatus includes a means for controllably adjusting the angular distribution of a molecular field effusing from a source material within the effusion cell, therein adjusting the flux of the beam. The method herein disclosed, with respect to the related apparati, including the step of selectively altering the angular distribution of an effusing molecular field, produced by a heated source material, which comprises the molecular beam, thereby varying the flux of the beam.
    Type: Grant
    Filed: April 29, 1996
    Date of Patent: February 3, 1998
    Assignee: Northrop Grumman Corporation
    Inventors: Myung B. Lee, Jari Vanhatalo
  • Patent number: 5709744
    Abstract: A method of masking surfaces during fabrication of semiconductor devices is disclosed, which includes providing a gallium arsenide substrate. The surface can include a layer of native oxide or not, and a metal mask is positioned adjacent the surface so as to define a growth area and an unmasked portion on the surface. Ultraviolet light is directed at the unmasked area, by exposing the surface to a bright light, so as to grow an oxide film on the unmasked portion of the surface. The metal mask is removed and the oxide film then serves as a mask for further operations and can be easily removed in situ by heating. If native oxide is included, it can be removed in situ by heating the substrate to a lower temperature.
    Type: Grant
    Filed: March 1, 1996
    Date of Patent: January 20, 1998
    Assignee: Motorola
    Inventor: Shiralagi Kumar