Abstract: The present application discloses a method for manufacturing shallow trench isolation, comprising: step 1: performing first time etching on a semiconductor substrate by means of a dry etching process to form the shallow trench, wherein in the first time etching, metal ions are released from a dry etching process chamber and deposited on the inner surface of the shallow trench, and the metal ions diffuse and form a contamination layer; and step 2: performing second time etching on the semiconductor substrate exposed on the inner surface of the shallow trench by means of a wet etching process to remove the contamination layer on the inner surface of the shallow trench. In the present application, the metal ions released from the dry etching process chamber and deposited on the inner surface of the shallow trench during the dry etching of the shallow trench can be removed.

Abstract: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric (IMD) layer, and first and second winding portions symmetrically arranged in the IMD layer and the insulating redistribution layer with respect to a symmetrical axis. The first and second winding portions each includes at least first and second semi-circular stacking layers arranged from the inside to the outside and in concentricity. The first and second semi-circular stacking layers each has a first trace layer in the insulating redistribution layer and a second trace layer in the IMD layer and correspondingly formed below the first trace layer. A first slit opening passes through the second trace layer and extends in the extending direction of the length of the second trace layer.

Abstract: A method includes forming an etch stop material layer and a planar sacrificial spacer layer over a front surface of a first substrate, forming an insulating encapsulation layer over the planar sacrificial spacer layer and on a backside surface and a side surface of the first substrate, forming a continuous structure including first semiconductor devices over a top surface of the insulating encapsulation layer, etching inter-die trenches within the continuous structure to divide the continuous structure, bonding the divided continuous structure to second semiconductor devices located over a second substrate, selectively removing the planar sacrificial spacer layer by performing a wet etch process in which an isotropic etchant is introduced into the inter-die trenches, and detaching the first substrate from an assembly of the second substrate, the second semiconductor devices, and the divided continuous structure after the removing the planar sacrificial spacer layer.

Abstract: The present application discloses a semiconductor device with a decoupling unit. The semiconductor device includes a first tier structure including conductive features of positioned over a substrate, and a decoupling unit the first tier structure positioned between the conductive features; a first-tier-alignment mark positioned on the decoupling unit, and including a fluorescence material; a second tier structure positioned on the first tier structure and including conductive features positioned over and deviated from the conductive features of the first tier structure, and a decoupling unit of positioned over the first tier structure, and positioned between the conductive features of the second tier structure; and a second-tier-alignment mark positioned on the decoupling unit of the second tier structure, and including a fluorescence material. The decoupling units include a low-k dielectric material and respectively include a bottle-shaped cross-sectional profile.

Abstract: A sensor package structure is provided. The sensor package structure includes a substrate, a sensor chip, a ring-shaped wall, and a light-permeable layer. The substrate has a first surface and a second surface that is opposite to the first surface. The first surface of the substrate has a chip-bonding region and a connection region that surrounds the chip-bonding region, and the substrate has a plurality of protrusions arranged in the connection region. The sensor chip is disposed on the chip-bonding region of the substrate and is electrically coupled to the substrate. The ring-shaped wall is formed on the connection region of the substrate, and the protrusions of the substrate are embedded in and gaplessly connected to the ring-shaped wall. The light-permeable layer is disposed on the ring-shaped wall, and the light-permeable layer, the ring-shaped wall, and the substrate jointly define an enclosed space therein.