Abstract: An input/output channel apparatus includes a system bus controller for generating a memory read request and outputting a memory address. Generation of the memory read request is inhibited in response to a request inhibit instruction generated by a request-inhibit generating section. When a memory bank other than one accessed in response to the immediately preceding memory read request is accessed, the request-inhibit instruction is generated. The request-inhibit instruction is canceled when memory interleaved data on the basis of the memory read requests for the same memory bank are input to a buffer in the apparatus.

Abstract: Backup battery switching circuitry for a microcomputer or a microprocessor includes circuitry for selectively coupling a backup battery to a power supply output terminal of the microcomputer or microprocessor for powering an external circuit such as a static RAM. The backup battery voltage is normally coupled to the power supply output terminal in the absence of a primary power source, but may be isolated from the power supply output terminal when a predetermined voltage is applied to a logic input pin and a predetermined sequence of events is executed by the microcomputer or microprocessor.

Abstract: A word processing apparatus is capable of logotype printing with a standard dot matrix pattern, and is controlled as to provide zero spacing between characters at logotype printing.

Abstract: A data processing apparatus includes a self-running type shift register and this shift register includes a plurality of latch registers arranged in a cascade fashion. The latch register latches a data packet on a word basis. In each latch register, a coincidence element is disposed in association therewith and these coincidence elements allow transfer of data from a post-stage latch register provided that a pre-stage latch register is vacant. A data processing element is installed between two latch registers and the data processing element processes operand data from either or both of the two latch register in response to the kind of processing shown by an operation code comprised in the preceding word. The result of processing is transferred to the pre-stage latch register when the pre-stage latch register is placed in the vacant state under control of the coincidence element.

Abstract: A unit for providing an interface between analog input signals and a digital data processing system bus includes a plurality of analog input channels, sample-and-hold circuits, and an analog-to-digital converter. An optical isolation circuit couples the output of the analog-to-digital converter to a dual-port RAM. The gain of each analog input channel is programmable, as is the address of each input channel in the RAM. Thus the channels can be read in any desired order, and different input voltage ranges can be programmed for each channel. The RAM can be read by an external data processing system via a digital system bus.

Abstract: A system (10) for scheduling serial message transmission on a single bus (11) having a plurality of messages to be sent stored in memory (21) with each message located between associated start and end message addresses (START, END). A message list or queue (28) of the messages to be sent is formed and stored in memory (22) wherein the list comprises message pointer blocks (27) associated with each of the messages. Each pointer block includes at least the message start and end addresses, the message unique ID code (MID), the message priority (PRI), the address of the message pointer block associated with the next message to be sent (NEXT) and the address of the message pointer block associated with the previous message to be sent (PREV). A message transmission apparatus (16, 17, 18, 19) then sequentially serially transmits the messages on the bus in accordance with the message transmission order specified in the message list.

Abstract: A word processing apparatus is capable of detecting the entry of a function or operation during keying of the text into memory, which requires an operator intervention such as the changing of the print element or the changing of the format parameters. Upon the detection of that condition, an automatic operation is invoked by the software process to insert into the text string and memory a stop code. This insures that the playout of the stored text will be interrupted to permit the operator to perform the same or related operation at the same relative position in the text.

Abstract: An automatic transfer switch with microprocessor and a display which includes clusters or combinations of display cells. There may, for example, be sixteen display cells for a 16-word display. The display cells are driven by two serially connected shift registers, the input of the first of which is interconnected with the microprocessor. Sixteen digital words are supplied in sequence to the shift registers. One portion of the digital word is then provided in parallel to each of the display cells simultaneously but another portion of the word is supplied to an encoding device which tells which of the sixteen display cells will display that word. One 16 word message requires sixteen reiterations performed at high speed so that it appears that all sixteen display devices are actuated simultaneously to display one multi-word message.

Abstract: A microinstruction sequencer capable of directing an arithmetic-logic unit to conduct conditional operations is disclosed and generally includes a ROM and a selection circuit. The ROM has a memory of m bits wide and n words long, wherein for an m bit wide word in the ROM which defines a conditional operation, a first plurality of bits of the m bits are allocated to a first set of bits for instructing the arithmetic-logic unit as to the function it is to perform, a second plurality of bits of the m bits are allocated to a second set of bits for instructing the arithmetic-logic unit as to the function it is to perform, and a third plurality of bits of the m bits are allocated to a set of control bits. The selecting circuit selects one set of bits from at least the first and second set of bits, and includes a controller for receiving the control bits and controlling the selection by the selection circuit in response thereto.

Abstract: A method for extracting and replacing Control Block information in an operating system. An extract replace table is provided to permit application programmers to locate and in certain instances replace items contained in operating system Control Blocks. The user of the application program need not know the precise location of information contained in operating system Control Blocks. The extract/replace table will, upon formulating a request for either extracting or replacing Control Block items, find the requested items and read or replace them. Revisions of operating system programs may be made without regard to the new location of control items. The system user will locate and replace Control Block items by addressing the updated extract/replace tables.

Abstract: In a monolithic semi-custom LSI, different types of standard LSI logic sections, each having a predetermined logic configuration and wiring pattern, and each serving as an independent LSI chip; glue circuits such as an SSI and an MSI which have design standards suitable for the same process conditions as those of the standard LSI logic sections, and which constitute a peripheral circuit section of the standard LSI logic sections; a mask pattern section having a wiring region for arbitrarily connecting terminals of the standard LSI logic sections and the peripheral circuit section, and a bonding pad section formed to surround the standard LSI logic sections and the peripheral circuit section to connect them to lead wires, are arranged to minimize the chip size. These constituting elements constitute common hardware as a master. The elements are connected through a single- or multi-layer wiring pattern.