Patents Examined by Florin Munteanu-Ramnic
  • Patent number: 4905183
    Abstract: A pattern generator permitting to output patterns at high speed and having an operating function, which is suitable for generating test patterns for memory ICs. Although it was known heretofore to increase the operating speed by operating a plurality of pattern generators, for which patterns were generated from memories, in which patterns were previously stored, in parallel, it was not possible to operate pattern generators having an operating function in parallel. A method, by which the order of execution of operation processing instructions is assigned to each of the pattern generators and operation processing instructions are accumulated and allows patterns to be generated at high speed by means of a pattern generator having an operating function. Specifically, the operating processing instructions are grouped and rearranged such that all the pattern generators execute instructions in parallel.
    Type: Grant
    Filed: July 29, 1987
    Date of Patent: February 27, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Ikuo Kawaguchi, Shuji Kikuchi, Chisato Hamabe
  • Patent number: 4901221
    Abstract: A method for programming a computer system having a display console for displaying images to control at least one of a virtual instrument and an instrument by the steps of displaying on the screen at least one first function-icon that references at least one first control module for controlling at least one first function; displaying on the screen at least one iteration-icon that references iteration control module for controlling multiple iterations of data flow; displaying on the screen at least one first input variable-icon that references at least one first input variable; displaying on the screen at least one first output variable-icon that references at least one first output variable; and assembling on the screen a first acyclic data flow diagram including the at least one first function-icon and the at least one iteration-icon and the at least one first input variable-icon and the at least one first output variable-icon, such that the diagram displays a first procedure for producing at least one value
    Type: Grant
    Filed: April 14, 1986
    Date of Patent: February 13, 1990
    Assignee: National Instruments, Inc.
    Inventors: Jeffrey L. Kodosky, James J. Truchard, John E. MacCrisken
  • Patent number: 4868783
    Abstract: A system for interconnecting an intelligent controller to a plurality of terminal devices includes a software module, a microprocessor and a device adapter having a plurality of output ports. The system operates under the control of said software module. When the system is powered up, a status for the output ports is assumed and tested under control of a configuration register. If the test is successful, the terminal port remains in that state; if unsuccessful, the state of the terminal port is reversed. The system permits an exchange of operating modes in the terminal devices associated with one port without adversely affecting operation of the remaining ports in the system.
    Type: Grant
    Filed: June 15, 1987
    Date of Patent: September 19, 1989
    Assignee: International Business Machines Corporation
    Inventors: Gary D. Anderson, Gerald J. Hladik, Lawrence G. Mosher, Raymond L. Ricci, Henry Yeh
  • Patent number: 4811275
    Abstract: An easily installable and easily expandable electromechanical memory assembly for a data processing system includes: a frame having a backplane, a plurality of printed circuit board connectors on the backplane, and conductors on the backplane which interconnect the connectors; a controller on a printed circuit board which is plugged into one of the connectors and consists essentially of logic circuitry for generating and receiving control signals on the backplane conductors; and multiple data storage units; each unit being mounted on a separate printed circuit board, plugged into a separate connector, and consisting essentially of a mechanical drive mechanism which reads data by physically moving a data storage medium past a data sensor in direct response to the control signals from the controller on the backplane conductors.
    Type: Grant
    Filed: May 28, 1986
    Date of Patent: March 7, 1989
    Assignee: Unisys Corporation
    Inventors: Edward Balogh, Jr., David D. Faultersack, Jack Peter, Stephen P. Roddy, Eric B. Thune
  • Patent number: 4805090
    Abstract: A storage module device-data link processor provides for management of data transfer operations between a main host computer system and up to eight separate disk drive units. The data link processor provides a peripheral interface circuit unit (for selection of a given disk drive unit) and which is connected to a formatter circuit unit and a host adapter access circuit unit. The formatter unit establishes the required protocol format for addressing and accessing a particular cylinder, a particular head track and a particular sector within the selected disk drive unit. The host access unit connects the data link processor to the main host computer while also managing execution of the data transfer operations, including error correction and integrity checking.
    Type: Grant
    Filed: September 27, 1985
    Date of Patent: February 14, 1989
    Assignee: UNISYS Corporation
    Inventor: Ronald S. Coogan
  • Patent number: 4788641
    Abstract: A magnetic tape system includes a driving unit (1) including a magnetic head (14), reels (11, 12) for winding a magnetic tape (16) thereon and a drive portion for driving the reels; a drive control unit (2, 20, 21) for controlling the drive unit; and a prefetch control unit (3) having a first memory for prefetching a plurality of commands from the host controller and a second memory for temporarily storing data from the host controller or data read out from the magnetic tape. The drive unit is operated through the drive control unit according to the commands stored in the first memory and the results of the operation are reported to the host controller.
    Type: Grant
    Filed: August 19, 1986
    Date of Patent: November 29, 1988
    Assignee: Fujitsu Limited
    Inventors: Masayuki Ishiguro, Noboru Ohwa
  • Patent number: 4788642
    Abstract: A bus control system for a common data bus between a central processing unit (CPU) and a plurality of peripheral devices has an address decoder which decodes address data from the CPU to output one of a chip selection signal S.sub.c and a plurality of chip selection signals S.sub.1 to S.sub.n. The chip selection signal S.sub.c brings all the devices into operative conditions simultaneously, while each of the chip selection signals S.sub.1 to S.sub.n brings a respective one of the devices into an operative condition. Each of the devices has a first register which is responsive to a corresponding one of the chip selection signals S.sub.1 to S.sub.n to store data appearing on predetermined bit-lines of the data bus and first and second gate circuits. When the CPU causes the address decoder to output the chip selection signal S.sub.c in a write mode, the first gate circuit of each device passes data appearing on the bit-line of the bus designated by the data in the first register into a second register.
    Type: Grant
    Filed: July 16, 1986
    Date of Patent: November 29, 1988
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventors: Satio Suzuki, Yasuhito Kawakita, Koichi Kaneko
  • Patent number: 4646261
    Abstract: In a system including a central processor, central memory, and local video controller communicating with a video terminal, the video terminal including a terminal processor and a video memory for storing video information for displaying on the terminal screen, a change detect circuit is provided in the local video controller for detecting whenever a change has occurred in that portion of the central memory containing video information to be displayed on the terminal's video screen. Responsive to the change detect circuit, the local video controller sends updated video information to the video memory at the terminal.The change detect circuit reduces the workload on the system by sending only the updated video information to the terminal.The change detect circuit is capable of operation with a system employing multiple terminals each having multiple independent screen display areas.
    Type: Grant
    Filed: September 27, 1983
    Date of Patent: February 24, 1987
    Assignee: Motorola Computer Systems, Inc.
    Inventor: Ed C. Ng
  • Patent number: 4642760
    Abstract: In a status-change gathering apparatus wherein status-change data is supplied to a processor from a plurality of inputting devices having a function of detecting status changes in a process or the like, each of the inputting devices is capable of producing an enable signal at a period not greater than the maximum allowed time between a detected status change in a controlled process and the controlling action to be performed by the processor, and of supplying the processor directly with an interrupt signal for requesting data gathering only when the enable signal is "on" and the status change has been detected. Upon receiving an interrupt signal from at least one inputting device, the processor sends a sense signal to all inputting devices, and any inputting device which has generated an interrupt signal places a response signal on a unique line to the processor to identify that inputting device. In this way, sequential scanning of inputting devices to detect changes in status is avoided.
    Type: Grant
    Filed: August 26, 1983
    Date of Patent: February 10, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Takao Yanai, Yoshiaki Takahashi
  • Patent number: 4602328
    Abstract: A system for the management of the physical memory of a processor which utilizes a base register which is loaded, for each virtual address of the memory, by a base address of a discriptive register corresponding to a task to be performed by the processor. This system utilizes a descriptive register table, an adder receiving the binary value of the base address of the first descriptive register, and the binary value of the index corresponding to the first register. The outputs of the adder address one of the inputs of the descriptive register table, thus selecting a segment descriptive register corresponding to the task to be performed. Each of the descriptive registers of the table contains control bits sent to the processor which makes it possible for the processor to check whether, for the segment to which the processor must have access, the processor must operate in the local or overall mode and whether the processor must process an input-output operation or an access to the memory.
    Type: Grant
    Filed: December 17, 1982
    Date of Patent: July 22, 1986
    Assignees: L'Etat Francais represente par le Ministre des P.T.T. (Centre National d'Etudes des Telecommunications), Institut National de Recherche en Informatique et en Automatique
    Inventors: Ulrich Finger, Pierre Ligneres, Ciaran O'Donnell
  • Patent number: 4601009
    Abstract: A memory system has a first memory such as a magnetic bubble memory and a second memory such as a RAM having a faster access time than the first memory. The first memory is divided into a plurality of blocks each of which has program steps stored therein. The second memory has a plurality of unit chains which correspond to the blocks of the first memory respectively and in each of which step information representative of the number of steps stored in the corresponding block and pointer information indicative of a connection to a next block are stored. The step information in the unit chains are successively read in accordance with predetermined start block information and the pointer information to count the total number of steps on the basis of the read step information. From the first memory is read information in the block corresponding to the unit chain of the second memory with respect to which the counting is made when the counted number of steps reaches or exceeds a program step number to be detected.
    Type: Grant
    Filed: September 8, 1983
    Date of Patent: July 15, 1986
    Assignees: Hitachi, Ltd., Hitachi Keiyo Engineering Co., Ltd.
    Inventors: Takashi Kogawa, Kazuyoshi Teramoto, Takeshi Hashimoto
  • Patent number: 4597058
    Abstract: A cartridge programming system is provided for loading selected computer programs into a reprogrammable plug-in cartridge memory. A host computer controls a plurality of remote programming terminals. The terminals contain a library of programs. The consumer can select one and have it loaded into a blank cartridge. The terminal verifies the integrity of the copy and records the transaction. The host can send new programs to the terminals via dial-up telephone lines and can request data on copying-transactions. Various security measures help assure accurate accounting of copies made, thereby assuring authors and their assignees that proper royalties can be billed.
    Type: Grant
    Filed: June 3, 1983
    Date of Patent: June 24, 1986
    Assignee: Romox, Inc.
    Inventors: Hideki D. Izumi, Devender R. Beravol