Abstract: A communications control system in a multi-processor system includes a connection distribution data structure, including, for each central processing unit, a connection count means for storing a number representing the number of communication connections currently being executed by the corresponding central processing unit, and a gate driver interface service module. The gate driver interface service module is a single task resident in the computer system memory with an active invocation in a single central processing unit of the processing system. The gate driver interface service module responds to each request by selecting the central processing unit presently executing the least number of communication connections, and assigning the communication connection to the central processing unit for execution by constructing a corresponding control block containing the identification of the central processing unit assigned to execute the communication operation.

Abstract: A serial communication port structure for starting and stopping an internal clock. This internal clock is designed, in operation, to generate a clock output signal to be transmitted to a device external to the system in which the serial communication port is incorporated. By ANDing the clock output signal with a data output signal of predetermined length, the serial communication port can effectively control the passage of time as sensed by the external device.

Abstract: In an arrangement for synchronizing data and other information in a computerized system which comprises a common serial data communication channel (212), two or several collaborating units (201) are arranged connectable to the channel, wherein a respective unit comprises a clock (207). A main clock is included in the system and the clock in one of the units can be used as main clock. The units with associated communication element and communication channel are arranged in such a manner that the time of the main clock can be transferred to the clocks of the other units. The clocks are arranged so that they can operate with a common time base. The units/communication elements comprise hard- and software or hardware which brings about the setting of a respective clock with predetermined accuracy in dependence on the main clock time.

Abstract: A method and apparatus is disclosed for partitioning a data buffer to create separate read and write buffers, wherein the boundaries between the buffers and the sizes of the buffers change dynamically depending upon the command mix received from the host computer. Data buffer space is allocated to provide highest priority to processing the current host command, and next priority to preserving a read ahead cache.

Abstract: Livelock-free message routing is provided in a network of interconnected nodes that is flushable in time T. An input message processor generates sequences of at least N time intervals, each of duration T. An input register provides for receiving and holding each input message, where the message is assigned a priority state p during an nth one of the N time intervals. At each of the network nodes a message processor reads the assigned priority state and awards priority to messages with priority state (p-1) during an nth time interval and to messages with priority state p during an (n+1) th time interval. The messages that are awarded priority are output on an output path toward the addressed output message processor. Thus, no message remains in the network for a time longer than T.

Abstract: An integrated circuit ("IC") interfaces a piece of communications equipment to a MIL-STD-1553 bus in accordance with the MIL-STD-1553 interface standards and operates in the MIL-STD-1553 defined bus controller mode of operation. The IC implements a command block configuration of data storage locations in an external memory. The command block includes a plurality of words arranged contiguously, a first word indicative of one of a plurality of different opcodes that define operation of the IC. The command block words include a MIL-STD-1553 defined command to be transmitted on the bus by the IC. A plurality of command blocks are arranged contiguously in a minor frame format. In order to sequentially execute a plurality of minor frames at different frequencies, the IC contains an internal timer that controls execution time of each minor frame.

Abstract: A bus interface for connecting two busses. It includes a first and second bus interface circuitry, central buffer and control circuitry. The control circuitry includes two control sequence circuitry for tracking and controlling the channels of data within a FIFO device. The sequence control circuitry includes a circular queue for providing a predetermined number of slots, each slot capable of containing the identity and the status of the channel of data already resident in the FIFO device, and capable of containing the identity of the channel of data pending residence in the FIFO device. The sequence control circuitry further includes two pointers for traversing the circular queue, slot by slot.

Abstract: A store-and-forward architecture which stores and distributes information programs to subscribers includes: information warehouses which archive information programs and dispense information programs in segments to central offices in bursts; central offices which manage subscriber's requests for service and buffer segments of information programs for delivery to subscribers in real-time under the subscriber's interactive control; and customer premises equipment. The central offices employ CO buffers, and each CO buffer includes: processors, for administering internal buffer operations and processing subscribers requests based upon the service presentation script and a program presentation map; interfaces for providing external access; busses for internal transport; buffer storage for storing segments of information programs; and memory storage for storing the script and map.

Abstract: A navigational tool is disclosed for traversing information units stored in a memory of a computer system. The computer system has a monitor and a control device and operates according to a computer application program. The navigational tool has three modules. The first module independently tracks a path traversed by the computer system under the control of the application program through the memory which generates and organizes a sequence of nodes into a hierarchical representation of the path followed by the computer system through the memory. The second module displays the sequence of nodes on the monitor simultaneously with the display generated by the application program. The sequence of nodes is continuously and automatically updated as the computer system traverses the memory. The control device is used to select any one of the sequence of nodes displayed on the monitor.