Abstract: In some embodiments, a non-volatile memory device includes a control logic circuit configured to generate a program signal and an erase signal based on control signals, a voltage generator configured to generate a program voltage and an erase voltage based on the program signal and the erase signal, a memory cell array including a memory cell, a string select transistor coupled to the memory cell, a bit-line coupled to the string select transistor, and a string select line coupled to the string select transistor, and a page buffer circuit coupled to the bit-line, and including a first precharge transistor that is configured to operate based on the program signal and the erase signal. The first precharge transistor is configured to apply the program voltage and the erase voltage to the bit-line in response to the program signal and the erase signal, respectively.

Abstract: A system includes integrated circuit (IC) dice and a processing device that retrieves a first block group to be written to the IC dice, the first block group being a contiguous portion of a file and associated with a first stream ID. In response to determining there is allocable space available in a first group of memory cells assigned to the first stream ID, identify a write pointer of the first group and allocate, within the first group, a contiguous range of physical addresses beyond the write pointer to which to write the first block group. The processing device retrieves a second block group to be written to the IC dice, the second block group associated with a second file, allocates the second block group to a second group of the memory cells, and assigns a second stream ID associated with the second group to the second block group.

Abstract: A computing-in-memory array, chip and electronic device includes a computing-in-memory array including at least one computing-in-memory cell having a first switch, a second switch, a third switch, a fourth switch, a coupling capacitor, a first bitline, a second bitline, a third bitline, a first wordline, a second wordline and a third wordline; a control module connected to the computing-in-memory array, which controls the voltages of each wordline and bitline to read and write data through the computing-in-memory array, or to perform computing-in-memory operations. By arranging the first switch, the second switch, the third switch, and the fourth switch in a differential form, and determining the stored value by the difference of the voltage between the two ports of the second switch and the third switch, the present embodiment of the disclosure can implement computing-in-memory operations with high accuracy, low circuit complexity, high reliability, and high energy efficiency.

Abstract: A storage device includes a nonvolatile memory device and a storage controller. The nonvolatile memory device includes a first memory region having a first write speed and a second memory region having a second write speed different from the first write speed. The storage controller includes an internal buffer and stores data from an external host in the first memory region by priority in a first mode. The storage controller controls a data migration operation by performing a read operation-transfer operation to read a second data that is pre-stored in the first memory region by a first unit and to transfer the first unit of data to a data input/output (I/O) circuit of the nonvolatile memory device a plurality of times and by storing the second data transferred to the data I/O circuit in the second memory region.

Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The controller is configured to make informed use of errors by update zone metadata to indicate one or more first logical block addresses were skipped and to indicate the next valid logical block address is available to store data. The controller is further configured to update zone metadata to recommend to the host device to reset one or more full zones, to recommend to the host device to transition one or more open zones to a full state, to alert the host device that one or more open zones have been transitioned to the full state, and to notify the host device of the writeable zone capacity of each of the plurality of zones.

Abstract: Disclosed is a memory block refreshing method. The method includes storing a read command in a first register to queue read refresh operations in a case that the read command causes a read counter value to reach a read refresher threshold value, the read counter value indicating a number of read operations performed, adjusting the read refresher threshold value based on a number of first memory blocks corresponding to the queued read refresh operations to obtain a new read refresher threshold value, and performing a mover read operation for moving data from the first memory blocks to second memory blocks different from the first memory blocks upon determination that the read counter value has reached the new read refresher threshold value.

Abstract: Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.

Abstract: A processor includes a queue configured to hold a memory access instruction including one or more addresses, a contracted address generator configured to generate a contracted address by contracting bits of multiple addresses in a case where the memory access instruction includes the multiple addresses, a conflict detector configured to detect a conflict between the contracted address and the address held in the queue, and an access controller configured to control processes of the memory access instruction held in the queue, based on a detection result of the conflict detector.

Abstract: Recovery support techniques for storage virtualization environments are described. In one embodiment, for example, a method may be performed that comprises defining, by processing circuitry, a storage container comprising one or more logical storage volumes of a logical storage array of a storage system, associating the storage container with a virtual volume (vvol) datastore, identifying metadata for a vvol of the vvol datastore, and writing the metadata for the vvol to the storage system. Other embodiments are described and claimed.

Abstract: A technique includes allocating, by a memory manager, a first region of a memory. The allocation includes selecting a logically contiguous first lane of the memory. The first lane is associated with a first identifier. The allocation further includes selecting a logically contiguous second lane of the memory. The second lane is a child of the first lane, and the second lane is orthogonal to the first lane. The second lane is associated with a second identifier. The technique includes, responsive to a request to access the first region, managing, by the memory manager, the access to the first region based on the first identifier and the second identifier.

Abstract: Aspects of a storage device including a memory and a controller are provided. In certain aspects, the controller may determine that data stored on a first block satisfies a threshold data-error condition, the data comprising invalid data and valid data. For example, the first block may have a high ratio of valid data to invalid data that satisfies or exceeds a threshold value. In certain aspects, the controller may determine a close block boundary associated with the first block, wherein the close block boundary is configured to bifurcate the first block into a first portion and a second portion, wherein the first portion comprises the data. For example, the controller may determine a boundary defined by a data length, an indirection mapping unit, a physical program boundary, etc.

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the control method includes the steps of: receiving a settling command from a host device to configure a portion space of the flash memory module as a zoned namespace; receiving a write command from the host device to write data corresponding a first zone into a plurality of blocks of the flash memory module, wherein an access mode chose by the flash memory controller is determined based on a size of each zone and a size of each block.

Abstract: A method includes forming at least a portion of a first superblock using a first subset of blocks from at least one memory die of a memory sub-system and forming at least a portion of a second superblock using a second subset of blocks from the at least one memory die of the memory sub-system.

Abstract: A memory controller includes a buffer memory including memory banks, one or more host access units configured to perform an access to the buffer memory for a host, one or more memory access units configured to perform an access to the buffer memory for a memory device, and a processor configured to control an operation of the memory controller. The processor divides the memory banks into an external memory bank group for an external operation related to the host, and an internal memory bank group for an internal operation within a memory system. The host access units access the external memory bank group. The memory access units access the external memory bank group to perform the external operation, and access the internal memory bank group to perform the internal operation.

Abstract: A method performed by a controller of a solid-state drive (SSD) comprising splitting a logical to physical mapping table in a non-volatile semiconductor memory device of the SSD into a plurality of regions, each of the regions associated with a plurality of logical cluster addresses (LCAs), determining if the mapping table for each region contains an entry with a valid address, setting a validity status in a validity bit for a region of the plurality of regions if the mapping table for the region contains any mapped addresses, and storing the validity bit for each region in a validity bitmap table (VBT).

Abstract: A method includes determining that a ratio of valid data portions of a block of memory cells is greater than or less than a valid data portion threshold and performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions is greater than the valid data portion threshold. The method further includes performing a second media management operation on the block of memory cells in response to determining that the ratio of valid data portions is less than the valid data portion threshold.

Abstract: A memory system includes a plurality of memory devices including first and second memory devices and a controller coupled to the plurality of memory devices to control operations performed on the plurality of memory devices. Each of the first and second memory devices includes a plurality of memory blocks, and memory blocks of the first and second memory devices form superblocks. The superblocks include a first superblock that includes memory blocks of the first and second memory devices and a second superblock that includes memory blocks of the first and second memory devices. The controller includes a first core unit and a second core unit configured to perform a first search operation and a second search operation, respectively, wherein the first and second search operations are performed in parallel.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.

Abstract: A processing load is reduced when a flash memory is used. A storage management device acquires an archive associated with an application, stores the acquired archive to one or more blocks among a plurality of blocks contained in the flash memory, and deletes one block among the plurality of blocks. In the archive storage, the acquired archive is stored in one of the blocks not storing an archive associated with an application different from that of the acquired archive, and in the deletion of one block, when an application is deleted, a block storing an archive associated with the application to be deleted is deleted.

Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.