Abstract: A method includes determining that a ratio of valid data portions of a block of memory cells is greater than or less than a valid data portion threshold and performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions is greater than the valid data portion threshold. The method further includes performing a second media management operation on the block of memory cells in response to determining that the ratio of valid data portions is less than the valid data portion threshold.

Abstract: A processing load is reduced when a flash memory is used. A storage management device acquires an archive associated with an application, stores the acquired archive to one or more blocks among a plurality of blocks contained in the flash memory, and deletes one block among the plurality of blocks. In the archive storage, the acquired archive is stored in one of the blocks not storing an archive associated with an application different from that of the acquired archive, and in the deletion of one block, when an application is deleted, a block storing an archive associated with the application to be deleted is deleted.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.

Abstract: A memory system includes a plurality of memory devices including first and second memory devices and a controller coupled to the plurality of memory devices to control operations performed on the plurality of memory devices. Each of the first and second memory devices includes a plurality of memory blocks, and memory blocks of the first and second memory devices form superblocks. The superblocks include a first superblock that includes memory blocks of the first and second memory devices and a second superblock that includes memory blocks of the first and second memory devices. The controller includes a first core unit and a second core unit configured to perform a first search operation and a second search operation, respectively, wherein the first and second search operations are performed in parallel.

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

Abstract: A storage device performing a secure erase and an operating method thereof are provided. The storage device may include a controller configured to control a non-volatile memory device including a plurality of blocks. The controller includes a secure erase control logic configured to control a secure erase operation on the plurality of blocks and perform a control operation in response to a secure erase request from a host with respect to a first block among the plurality of blocks such that the secure erase operation on the first block is skipped based on a result of determining at least one selected from a secure erase state and/or a deterioration state of the first block.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, the memory system may, with respect to data stored in the memory device, write the data to a first target memory block or a second target memory block among the plurality of memory blocks according to whether a data type of the data is a read-intensive type or a write-intensive type.

Abstract: Variable Capacity Zone Namespace (ZNS) Flash Storage Data Path. In one example, a data storage device including an electronic processor that, when executing a variable capacity scheme, is configured to determine whether a special indication regarding a particular zone in a ZNS is received, delay an association of a final flash block with the particular zone, receive and stage host data for the particular zone in a staging area, receive a zone close request, compact the host data with other host data for storage in other zones into second host data, and move the second host data to the final flash block that is associated with the particular zone and the other zones. The compaction of the host data with the other host data into the second host data reduces or eliminates padding in the final flash block, and consequently, reduces overhead in the data storage device.

Abstract: A data storage environment can include one or more virtual machines instantiated on a host computing device. Based on physical location data of the one or more virtual machines received from the host computing device, a storage manager can control the performance of a secondary copy operation on one or more storage units that store virtual machine data associated with the one or more virtual machines and/or the performance of a secondary copy operation on the one or more virtual machines.

Abstract: Systems and methods that make use of cluster-level redundancy within a distributed storage management system to address various node-level error scenarios are provided. Rather than using a generalized one-size-fits-all approach to reduce complexity, an approach tailored to the node-level error scenario at issue may be performed to avoid doing more than necessary. According to one embodiment, responsive to identifying a missing branch of a tree implemented by a KV store of a first node of a cluster of a distributed storage management system, a branch resynchronization process may be performed, including, for each block ID in the range of block IDs of the missing branch (i) reading a data block corresponding to the block ID from a second node of the cluster that maintains redundant information relating to the block ID; and (ii) restoring the block ID within the KV store by writing the data block to the first node.

Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; identify, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block; identify, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.

Abstract: A method includes determining that a criteria involving a memory device is met and performing a defect scan involving memory dice of the memory device in response to the criteria being met. The method further includes determining, as part of performing the defect scan, whether at least one memory die of the memory device has experienced degradation. The defect scan is performed as part of a quality and reliability assurance test or a reliability demonstration test, or both.

Abstract: Apparatus and methods are disclosed, including a sequential mapping table located within a flash memory array of a flash memory device. Selected examples include firmware in the flash memory device to load the sequential mapping table into a cache upon power and perform read and write operations using the sequential mapping table. Selected examples include firmware in the flash memory device to store an updated sequential mapping table into the flash memory array upon power down of the flash memory device.

Abstract: Disclosed are a controller that controls a memory device, and an operating method of the controller. The controller may include a host interface suitable for fetching a write command received from a host; and a processor suitable for controlling a write operation of the memory device in response to the fetched write command, wherein, when a workload of a background operation of the processor is greater than a workload of a host write operation, the host interface is further suitable for: determining a delay amount of time and providing the host with a completion response to the write command after delaying the completion response by the delay amount of time.

Abstract: An electronic device includes one or more processors for executing one or more virtual machines. In response to a request for initiating a synchronization event, a processor identifies a subset of speculative memory access requests in one or more memory access request queues. Automatically and in accordance with the identifying, the processor purges translations associated with the subset of speculative memory access requests. Subsequent to the purging, the processor initiates the synchronization event. In some implementations, memory access completion is forced in response to a context synchronization event that corresponds to a termination of a first application, a termination of a first virtual machine, or a system call for updating a system register. Alternatively, in some implementations, memory access completion is forced in an operating system level or an application level in response to a data synchronization event that is initiated on a hypervisor layer or a firmware layer.

Abstract: A controller controls a semiconductor memory device including a plurality of memory blocks. The controller includes a block manager, a map data manager, and a command generator. The block manager manages information on the plurality of memory blocks. The map data manager manages map data for data stored in the plurality of memory blocks. The command generator generates a program command for controlling a program operation of the semiconductor memory device. The command generator generates a program command for storing data in a first memory block among the plurality of memory blocks, and determines a second memory block to store dummy data based on information from the block manager when the first memory block is full by a program operation corresponding to the program command.

Abstract: In some examples, a system may include a plurality of memory blocks, a first data bus coupled to the plurality of memory blocks in a memory device, a second data bus coupled to the plurality of memory blocks, a controller configured to perform memory read and write operations on the plurality of memory blocks via the first data bus, and a non-volatile storage (NVS) data transfer circuit configured to transfer data in a first memory block of the plurality of memory blocks to a NVS device via the second data bus. The first memory block may be a cold data block least accessed among the plurality of memory blocks. The cold data transfer may be performed via the second data bus when a different memory block is being accessed via the first data bus concurrently. The second data bus may be a fuse bus in the memory device.

Abstract: A heterogeneous processor system includes a first processor implementing an instruction set architecture (ISA) including a set of ISA features and configured to support a first subset of the set of ISA features. The heterogeneous processor system also includes a second processor implementing the ISA including the set of ISA features and configured to support a second subset of the set of ISA features, wherein the first subset and the second subset of the set of ISA features are different from each other. When the first subset includes an entirety of the set of ISA features, the lower-feature second processor is configured to execute an instruction thread by consuming less power and with lower performance than the first processor.

Abstract: The present disclosure generally relates to methods and systems for allocating free blocks as decommissioned blocks to replace bad blocks. In certain embodiments, when there are insufficient free blocks in a free block list to replace a bad or defective block for a CE, an FTL scans blocks stored in an unallocated block repository. If there are unallocated blocks available for the CE, one or more is reallocated as free blocks and used to replace the bad or defective block. When only one or no further unallocated blocks for the CE are available, the FTL places the CE in a read-only mode.