Abstract: A semiconductor memory device and operational method having reduced well noise are provided. The memory device includes a plurality of memory cells arranged in rows and columns within an array well and addressable by a plurality of word lines and bit lines. The array well is biased to a desired potential and a sense amplifier is employed to read bit line states during a predefined bit line signal development period. Array well biasing is removed during at least a portion of this signal development, so that the well potential floats (ideally remaining stable) as signals are being developed on the bit lines. This temporary, floating well technique is particularly important for open bit line architectures.

Abstract: A semiconductor memory device including: a memory cell array having at least one cell array unit, the cell array unit including a plurality of memory cells; a decoder for selecting at least one the memory cell in accordance with an externally supplied address; an input/output terminal for outputting data read from the selected memory cell and for receiving data supplied externally and sending the data to the selected memory cell; at least one data line for connecting the input/output terminal to each the cell array unit; sense amplifiers serially connected to each the data line in a multiple stage configuration for amplifying the read data; a write buffer connected in parallel with one of the sense amplifiers connected to each data line; by-pass switching elements connected between input and output terminals of the other sense amplifiers connected to each the data line; and a control circuit for applying an on-signal to at least one by-pass switching element when writing data, the on-signal turning on at leas

Abstract: A memory stores data in a first-in-first-out order and associatively matches an incoming datum with the stored data. The stored data includes a first datum and a second datum stored following the first datum. The memory includes a data storage cell which comprises a memory cell coupled to a bit line and a word line. The memory cell stores the first datum. The memory cell can be accessed through the bit line and the word line for read and write operation. The memory cell includes a first half and a second half connected to each other. An exclusive NOR gate circuit is coupled to an output of the memory cell and the bit line for associatively comparing the first datum stored in the memory cell with an incoming datum along the bit line. The exclusive NOR gate circuit outputs a match signal when the incoming datum matches the first datum.

Abstract: A refresh timer suitable for use in a semiconductor memory device which has a refresh mode of operation which is enabled by a refresh enable clock signal, and which utilizes an operating voltage having a plurality of different operating levels, Vi, where i=1-n, and n is an integer equal to or greater than two. The refresh timer includes a first circuit responsive to the operating voltage for generating a plurality of output voltage signals corresponding to the plurality of different operating voltage levels, respectively. The first circuit includes a plurality of individual voltage detection circuits corresponding to the plurality of different operating voltage levels, respectively, with each ith one of the voltage detection circuits being adapted to detect whether the operating voltage is at the corresponding ith level, and to drive the corresponding ith one of the output voltage signals high when it is detected that the operating voltage is at the corresponding ith level.

Abstract: A programmable read-only memory device and method of fabrication are disclosed having an antifuse in the drain node of a field effect transistor. Programming is accomplished by imposing a high voltage on the transistor drain and gate which causes the antifuse to be a closed circuit; otherwise, the transistor appears as an open circuit. Locating the antifuse in the drain node as opposed to the source node avoids problems of source reverse bias.