Patents Examined by Frank R. Niranjan
  • Computer including an integrated circuit having a low power selection control arrangement
    Patent number: 5301160
    Abstract: A computer system includes a data processor; an address bus; a data bus; row and column decoding circuits; an integrated circuit memory device interconnected with the data processor by way of the address and data buses, the memory device having a pair of bitlines including parts, a sense amplifier, selectable transfer gates between the bitline parts and sense nodes of the sense amplifier, a selection circuit that enables transmission through the transfer gates in response to address signals. The selection circuit provides either a precharge voltage to the transfer gates during a precharge state or high and low level signals to the transfer gates when selecting a transfer gate. During transition to the precharge state, a charge transfer path is enabled for transferring charge from one transfer gate lead to another transfer gate lead. Thereby a substantial quantity of charge is conserved during operation.
    Type: Grant
    Filed: February 24, 1992
    Date of Patent: April 5, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Hugh P. McAdams
  • PROM IC with a margin test function
    Patent number: 5297101
    Abstract: A PROM IC including sense circuits, each including a sense amplifier. A pull-up resistor circuit whose resistance value is variable is provided on the side of an input of the sense amplifier so that, upon a reception of a test selection signal, the resistance value of the resistor circuit is changed to a value with which a drive condition of current flowing through a selected memory cell becomes severe.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: March 22, 1994
    Assignee: Rohm Co., Ltd.
    Inventors: Yoshihiro Tada, Hiromi Uenoyama
  • Memory having distributed reference and bias voltages
    Patent number: 5291455
    Abstract: A memory (20) has N.sub.BIAS generators (63 and 73) coupled to the positive and negative power supply lines (61 and 62) at a point close to amplifiers (84 and 85) and address buffers (76) to insure that they all receive the same power supply voltage to prevent an impact on the access times of memory (20). A V.sub.CS generator (65) is located close to power supply bonding pads (23 and 25) and to output buffers (77 and 78) to reduce the effects of power supply line noise on the noise margins. A V.sub.AREF generator provides a reference voltage to the differential amplifiers of address buffers (75 and 76). Locating V.sub.AREF generator (67) close to power supply bonding pads (23 and 25) insures that the reference voltage is always at the midpoint of the input logic swing.
    Type: Grant
    Filed: May 8, 1992
    Date of Patent: March 1, 1994
    Assignee: Motorola, Inc.
    Inventors: Taisheng Feng, John D. Porter, Jennifer Y. Chiao