Patents Examined by Frazli Erdem
  • Patent number: 7145185
    Abstract: The invention concerns a voltage-controlled triac-type component, formed in a N-type substrate (1) comprising first and second vertical thyristors (Th1, Th2), a first electrode (A2) of the first thyristor, on the front side of the component, corresponding to a first N-type region (6) formed in a first P-type box (5), the first box corresponding to a first electrode (A2) of the second thyristor, the first box containing a second N-type region (8); and a pilot structure comprising, above an extension of a second electrode region (4) of the second thyristor, a second P-type box (11) containing third and fourth N-type regions, the third region (12) and a portion of the second box (11) being connected to a gate terminal (G), the fourth region (13) being connected to the second region (8).
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: December 5, 2006
    Assignee: STMicroelectronics S.A.
    Inventor: Jean-Michel Simmonet
  • Patent number: 6909141
    Abstract: A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on a base side thereof to a first common electrical contact. The vertical pillar structures include, along the vertical direction, layer zones of differing conductivity, and have insulation layers on their circumferential walls. An electrically conductive material is deposited between the pillar structures and forms a second electrical contact of the semiconductor transistor component. The pillar structures are electrically contacted to a third common electrical contact on their capping side.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: June 21, 2005
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Rösner, Thomas Schulz, Lothar Risch, Thomas Äugle, Herbert Schäfer, Martin Franosch
  • Patent number: 6608371
    Abstract: A method of manufacturing a semiconductor device includes: a first step of forming a first through hole that penetrates the location of the electrode in a semiconductor element having an electrode; a second step of providing an insulating material in a region including an inside of the first through hole, in such a manner that a second through hole is provided penetrating through the insulating material; and a third step of providing a conductive member within the second through hole that penetrates through at least the insulating material in the inside of the first through hole.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: August 19, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Yohei Kurashima, Kazushige Umetsu, Haruki Ito