Abstract: An apparatus for facilitating the sharing of memory blocks, which has local physical addresses at a computer node, between the computer node and an external device. The apparatus includes snooping logic configured for coupling with a common bus of the computer node. The snooping logic is configured to monitor, when coupled to the common bus, memory access requests on the common bus. There is also included a snoop tag array coupled to the snooping logic. The snoop tag array includes tags for tracking all copies of a first plurality of memory blocks of the memory blocks cached by the external device. Further, there is included a protocol transformer logic coupled to the snooping logic for enabling the apparatus, when coupled to the external device, to communicate with the external device using a protocol suitable for communicating with the external device.

Abstract: An information recording/reproducing apparatus for recording or reproducing information on or from a recording medium in response to a command sent from a host computer has a cache memory serving as an intermediate memory and temporarily storing information to be transferred to or from the host computer. In response to an information record command sent from the host computer, completion of writing of information is reported to the host computer at the end of storing record data transferred from the host computer in the cache memory. The record data stored in the cache memory is written on a recording medium independently of data transfer between the host computer and intermediate memory. In response to an information playback command sent from the host computer, it is determined whether playback data requested by the host computer is consistent with unprocessed record data stored in the cache memory.

Abstract: A prefetch operation greatly reduces the amount of delay between the transmission of a peripheral device request and the receipt of an I/O card acknowledge for peripheral read data, for example in a network printer environment where the amount of time required to transfer print data from an I/O card to a printer is reduced which, in turn, reduces the amount of time required for the printer to process a print job. The communication protocol between a peripheral device and an I/O card is typically based on a packet data structure, which consists of a header that contains the starting address of the buffer, the data length, and maximum data length of the packet buffer fields which are used for the information transfer between the I/O card and peripheral device; and a buffer for transferring data or messages between the peripheral device and the I/O card. The prefetch operation reduces the possibility of shared memory contention by prefetching the next requested data.

Abstract: A coherence transformer for allowing a computer node and one or more external devices to share memory blocks having local physical addresses at a memory module of the computer node. The coherence transformer includes logic for ascertaining whether a memory access request from the external device for a memory block should be responded to using a snoop-only approach or an Mtag-only approach. The snoop-only approach requires a tag in a snoop tag array of the coherence transformer be available to track the memory block for an entire duration that the memory block is cached by the external device. The Mtag-only approach only temporarily stores the memory block until a global state associated with the memory block can be written back into the memory module of the computer node. The snoop tag array allows the coherence transformer to snoop the bus of the computer node to intervene and respond to memory access requests pertaining to a memory block externally cached and tracked by the snoop tag array.

Abstract: A microprocessor is provided including a pair of caches and a dependency checking structure for accesses between the pair of caches. One of the pair of caches is accessed from the decode stage of the instruction processing pipeline, while the other is accessed from the execute stage. The dependency checking structure monitors for memory dependencies between accesses to each of the pair of caches. Memory accesses may be performed earlier in the instruction processing pipeline than was previously achievable. Additionally, the dependency checking structure ensures that memory accesses receive the correct data by comparing accesses performed from each stage of the instruction processing pipeline to each other. In one embodiment, read and write dependency bits are stored by the cache which is accessed from the decode stage of the instruction processing pipeline. Decode stage accesses are recorded as a read or write by setting an associated dependency bit.

Abstract: In a method and system of performing a write cycle to a memory address in a multi-processor system, a first write cycle is initiated to the memory address, and a second write cycle is initiated to the memory address. Data from the first and second write cycles is merged, and the merged data is written to the memory address.

Abstract: An adaptive read ahead cache is provided with a real cache and a virtual cache. The real cache has a data buffer, an address buffer, and a status buffer. The virtual cache contains only an address buffer and a status buffer. Upon receiving an address associated with the consumer's request, the cache stores the address in the virtual cache address buffer if the address is not found in the real cache address buffer and the virtual cache address buffer. Further, the cache fills the real cache data buffer with data responsive to the address from said memory if the address is found only in the virtual cache address buffer. The invention thus loads data into the cache only when sequential accesses are occurring and minimizes the overhead of unnecessarily filling the real cache when the host is accessing data in a random access mode.

Abstract: A memory control and management system efficiently multiplexes access to a dynamic random access memory (DRAM) among several client processes in an MPEG or similar digital television delivery system or the like. These processes can include, for example, an on-screen display (OSD) graphics processor, a microprocessor interface, graphics accelerator functions, and audio and data processors. An arbiter receives packetized data from an MPEG transport layer for distribution to an associated DRAM. The arbiter sequentially time-multiplexes access to the DRAM by the client processes according to priority criteria, including the bandwidth requirements of the client processes, and whether a client process is requesting access. Access is granted for a predetermined period as long as the client is requesting access.

Abstract: A computer system which prevents unauthorized access to files within a memory such as a disk. A first software program within the computer attempting to access the files is authorized to access the files whereas another software program within the computer is not authorized to access the files. When the first software program desires to access the files and uses the appropriate password or key-code, the first software program is allowed access to the information whereas the second software program within the same computer is not allowed access to the information within the files. The files may be stored in a file server which is networked to a client computer containing the software programs. Alternatively, the files may be stored in an intelligent peripheral device which is not located within a conventional file server and the computer connected to the peripheral device includes the software programs which attempt to access the files within the peripheral device.

Abstract: An apparatus is programmed with a plurality of programming instructions for generating, if possible, an alternative disk block allocation for a current disk block allocation that will yield improved overall access time for a sequence of disk accesses. In some embodiments, the programming instructions include the logic for tracing the sequence of disk accesses to determine the current disk block allocation, the logic for generating the alternative disk block allocation, if possible, using the trace results, and the logic for effectuating the alternate disk block allocation, if generated. In one particular embodiment, the logic for generating the alternative disk block allocation employs a random search approach, while in another embodiment, the logic for generating the alternative disk block allocation employs a heuristic approach.

Abstract: A cache control apparatus for controlling address mapping of a cache memory which can dynamically change the mapping algorithm of the address mapping. The cache control apparatus has a plurality of mapping controllers individually provided for different mapping algorithms each for producing a set address and an address tag in response to an output of said address register, a mapping algorithm controller for selecting one of the mapping controllers and outputting a selector control signal, a first selector for selecting one of the set addresses outputted from the mapping controllers, a second selector for selecting one of the address tags outputted from the mapping controllers, a comparison circuit for comparing the address tags outputted from the second selector and a tag memory, a hit discrimination circuit for discriminating a cache hit based on a result of the comparison by the comparison circuit, and hit ratio calculation means for calculating a cache hit ratio.

Abstract: A computer network for high-speed data communication, has a data transmission cable with a root and at least one leaf node. A signal conversion system (SCS) is attached to the root, and at least one client station is attached to a leaf node. The SCS consists of a transmitter that transmits down-stream data onto said cable in a first frequency band; and a receiver that receives data from said client stations on a second frequency band; wherein said down-stream data includes synchronization and acknowledgement signals. Each client station has a receiver that receives data on said first frequency band, and a transmitter that transmits data on a second frequency band according to synchronization signals received on said first frequency band.

Abstract: A method and apparatus for interfacing a memory card with a system having a smaller bus width while maintaining its interchangeability with other systems having larger bus widths. The host accesses data stored in the memory card using an interleaving scheme, such as a two-way interleaving scheme. The host provides a first enable signal and a second enable signal. In response to the first enable signal, data is accessed from a first section of the addressed memory location, and in response to the second enable signal, data is accessed from a second section of the addressed memory location. The first section of the addressed memory location may store even data bytes and the second section of the addressed memory location may store odd data bytes. The host may only access one section of the selected memory location at a time when using the interleaving scheme.