Abstract: A designing apparatus comprises symbol mark memory for storing fluid controllers usable in fluid control devices in terms of symbol marks representing the functions, fluid channels and contours of the controllers, and a flowchart preparing device for preparing a flowchart of a fluid control device represented by symbol marks. The flowchart preparing device successively selects controllers, such as valves and massflow controllers, from a symbol mark file in the memory, arranges the selected controllers on a screen as suitably positioned, automatically selects a suitable coupling member for interconnecting adjacent two of the controllers from a coupling member data file and automatically arranges te controllers and the coupling members thus selected to prepare a flowchart.

Abstract: A method for analyzing and designing structures with structural aliasing. The concept of structural aliasing applies in one embodiment of the present invention to structural systems which are cyclically symmetric. In analyzing and designing structural systems such as wheel assemblies of gas turbine engines, it is possible to group the discrete components so as to aliasingly couple particular ordered excitations and harmonic families. With structural aliasing, it is possible to couple the ordered excitations and harmonic families such that resonant response of the wheel assembly does not occur within the operating range of the engine, and also to have the resonant vibratory mode excited in such a manner that the drive coupling of the wheel dampens the wheel assembly.

Abstract: A function for adaptively generating test vectors to verify the behavior of a digital system. The function utilizes one or more user-defined verification directives for directing the generation of the test vectors to areas of interest within the digital system. An emulator of the digital system provides dynamic feedback of internal state information to the test vector generation function during the verification. The test vector generation function adaptively generates future verification test vectors based on the user-defined verification directives in view of the internal state information feedback received from the emulator.

Abstract: Disclosed is a method of designing a memory device that has substantially reduced bitline voltage offsets. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The method also includes designing a six transistor core cell having a bitline and a complementary bitline, and designing a flipped six transistor core cell that has a flipped bitline and a flipped complementary bitline. Further, the method includes arranging a six transistor core cell followed by a flipped six transistor core cell along each of the multiple pairs of the global bitline and the global complementary bitline. Preferably, the bitline of the six transistor core cell is coupled with the flipped complementary bitline of the flipped six transistor core cell, and the complementary bitline of the six transistor core cell is coupled to the flipped bitline of the flipped six transistor core cell.