Abstract: In time diversity communication system, loss of data or generation of incorrect data may occur due to, for example, the shadow effect. In the present invention, on the transmission side, an interlaced signal is generated in which the input digital signal string is combined with the same signal string delayed by n bits, k redundancy bits are added to every m bits of this signal, the signal is divided into blocks of (m+k) bits, an interleaving process is executed for every j blocks in which unique words are added, following which the signal is transmitted. On the receiving side, unique words are detected, a de-interleaving process is performed, and a check is made for the presence of error signals. The delayed and non-delayed signals are next separated from the decoded data, and depending on the state of the signals, the desired signal is selected at selector 33 and outputted.

Abstract: The present invention helps derive accurate clock and carrier translation presets in the presence of noise and various line shapes. The invention provides an adaptive algorithm that optimizes the calculations of clock slew (.DELTA.T.sub.s) and frequency offset (.DELTA.f) over the specific line conditions encountered at each connection by choosing an optimal subset of the communication device's probing frequencies that minimizes the effect of line losses and noise.

Abstract: Disclosed is a digital multiplication circuit to multiply a digital signal SN by a periodic waveform that is, in principle, a sine waveform. This circuit uses a phase digital generator .phi. varying in saw-toothed form and it uses an approximation of the samples of a function K sine .phi. by algebraic sums of positive integer values of two for each phase value, K being a coefficient identical for all the phase values. The product of SN by these sums is rapid and easy to obtain and does not require a sine table. A decoder receiving the phase .phi. defines the powers of two to be set up, and a routing circuit carries out the operation of multiplication by powers of two under the control of the decoder. One or two adders obtain the sums of powers of two. The result is an approximate result of the product SN.K. sine .phi..

Abstract: Known is a receiver having a demodulator for intermediate frequency modulated frequency shift keyed signals. The known demodulator applies absolute period time measurements expressing the period of a divided IF-signal into clock pulses of a relatively high frequency reference clock to detect data from a received signal. Such a demodulator is sensitive to frequency drift of the reference clock and has a relatively large power consumption. A receiver is proposed having a demodulator that is arranged to transform the intermediate frequency modulated frequency shift keyed signal into a lower frequency modulated frequency shift keyed signal so that the relative frequency deviation representing the data becomes substantially larger.

Abstract: A carrier recovery apparatus includes a loop filter that converges quickly and corrects a large frequency error. The carrier recovery apparatus includes a multiplier, a matched filter, a phase error detector, a loop filter and a numerically controlled oscillator (NCO). A bandwidth varying circuit varies the bandwidth of the loop filter according to whether the signal output from the matched filter is phase-locked. A frequency error detector detects a frequency error from the output of the matched filter. An adder adds each level of an input sweep signal and the output of the loop filter, and supplies the added results to the NCO. A switch selectively supplies the output of the loop filter to the adder. A controller generates a sweep signal having a plurality of levels and controls turning the switch on and off.

Abstract: The invention relates to a method for detecting the beginning of time messages in the signal received from a time-signal transmitter. The signal of the time-signal transmitter consists of a series of blanking intervals on a carrier signal in the seconds clock cycle in which blanking intervals of different length cause different information units to be transmitted (ZERO pulse, ONE pulse, frame pulse). A time message, comprising the information units transmitted over a period of one minute, contains the actual time information in coded form. The time message has areas/sectors with defined, constant information units and areas/sectors with variable contents that code the time information. A reference message is stored in a first area of memory that contains the defined, constant information units that are located in fixed areas/sectors. A number of successive information units corresponding to the length of a time message are stored in a second area of memory.

Abstract: A speech encoding communication system for use with a land mobile radio telephone system which decreases an unfamiliar feeling to a sound output caused by a cyclic tone variation of background noise. On the transmission side, an audition weighting filter selectively receives a sound signal or an output of a low-pass filter for the sound signal in response to VOX mode information. In a sound absent condition based on the VOX mode information, a power quantizer outputs a power index calculated by an average of the power over a long period, and an LPC analyzer outputs a unique value as an LPC and an LSP quantizer outputs a quantized LSP index and a quantized LPC obtained when the LPC has the unique value in the sound absent condition. Further, an adaptive codebook search unit controls an adaptive codebook index to a unique value without performing searching processing. On the reception side, a power controller receives a quantized power, VOX mode information and a sound signal.

Abstract: In a sync detector, a baseband signal is segmented into a plurality of successive bit sequences so that the bits of each sequence are shifted by one bit position with respect to the bits of adjacent sequences. On a bit-by-bit basis, mismatches are detected between each input bit sequence and a predetermined bit sequence and the detected mismatches are counted to produce a mismatch count. A first comparison is made between the mismatch count and a reference value to determine that a sync code is detected if the mismatch count is equal to or smaller than the reference value, and a further comparison is made between successively produced mismatch counts to determine that a sync code is detected when the later of the successively produced mismatch counts is equal to or smaller than the earlier one. The first comparison is repeated when the later mismatch equals zero.

Abstract: A digital modulator having a pulse shaping filter which generates and accumulates impulse responses including prior impulse responses and posterior impulse responses to perform a Root-Nyquist raised cosine filtering. The pulse shaping filter includes a dummy accumulation data memory storing dummy accumulation values of prior impulse responses required for initial data transmission. When several initial impulse responses are to be transmitted, for example, on power-up, the impulse responses corresponding to input digital data are generated and added to the dummy accumulation values of prior impulse responses. After the initial transmission, the impulse responses corresponding to input digital data are generated and transmitted without the help of the dummy accumulation values.

Abstract: A cycle slip detector of the invention has first and second comparators. The first comparator determines that the value of a phase error signal being supplied thereto is larger than a first threshold value near a maximum value possibly taken by the phase error signal, and responsively generates a first determining signal. The second comparator determines that the value of the phase error signal being supplied thereto is smaller than a second threshold value of a minimum value possibly taken by the phase error signal, and responsively generates a second determining signal. The cycle slip detector generates a cycle slip detecting signal when the first determining signal and the second determining signal generate in succession. By applying the cycle slip detector as mentioned, it is possible to provide a phase locked loop circuit having a wide frequency range in which a withdraw or pull-in operation is permitted.

Abstract: An adaptive equalizer performs adaptive signal processing on an input digital signal passing through a transfer path so as to minimize an equalization error and sends out a digital signal obtained by the adaptive signal processing. This adaptive equalizer comprises: a variable coefficient filter for performing a filtering process on the input digital signal based on a coefficient set therein; an error detection system for detecting the equalization error; and a coefficient control section for controlling the coefficient based on the equalization error.

Abstract: A phase locked loop (PLL) circuit forming a closed loop and comprised of a frequency/phase detector, a loop filter, a voltage controlled oscillator and further includes a voltage controlled oscillator controller. The circuit realizes a faster frequency locking and is capable of outputting a variety of frequencies.