Patents Examined by Fritz Alphonse
  • Patent number: 10355717
    Abstract: An encoder signal processing device detects position data at every predetermined time interval from an original signal which is an analog amount generated in an encoder according to movement of a measurement target. The encoder signal processing device includes: an approximate curve calculation unit that calculates an approximate curve of a detection error included in the original signal on the basis of the detection error of the position data at at least three or more points; an approximate error computation unit that computes an approximate value of the detection error of the position data at an arbitrary time point on the basis of the approximate curve of the detection error; and a position data correction unit that corrects the detection error of the position data at the arbitrary time point on the basis of the approximate value of the detection error of the position data.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: July 16, 2019
    Inventor: Youhei Kondou
  • Patent number: 10355719
    Abstract: Information reduction in data processing environments includes at least one of: one or more Error Correcting Codes that decode n-vectors into k-vectors and utilize said decoding to information-reduce data from a higher dimensional space into a lower dimensional space. The information reduction further provides for a hierarchy of information reduction allowing a variety of information reductions. Transformations are provided to utilize available data space, and data may be transformed using several techniques including windowing functions, filters in the time and frequency domains, or any numeric processing on the data.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: July 16, 2019
    Inventor: Allan Havemose
  • Patent number: 10348333
    Abstract: Apparatus, methods, and systems are disclosed for performing bit error correction on a data stream. In some aspects, the described systems and methods may include a plurality of memory devices, a first interface, and a field programmable gate array. The field programmable gate array may include a memory controller and a plurality of re-programmable gates. At least one of the re-programmable gates may be configured as a read-only memory (ROM) to store a syndrome decode memory table, wherein the syndrome decode memory table may be configured to perform bit error correction on the data stream being read and/or written to at least one memory device of the plurality of memory devices via the first interface.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: July 9, 2019
    Assignee: Everspin Technologies, Inc.
    Inventor: Kurt Baty
  • Patent number: 10340949
    Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing LDPC base graphs. Two or more LDPC base graphs may be maintained that are associated with different ranges of overlapping information block lengths. A particular LDPC base graph may be selected for an information block based on the information block length of the information block. Additional metrics that may be considered when selecting the LDPC base graph may include the code rate utilized to encode the information block and/or the lift size applied to each LDPC base graph to produce the information block length of the information block.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: July 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Joseph Binamira Soriaga, Gabi Sarkis, Shrinivas Kudekar, Thomas Richardson, Vincent Loncke
  • Patent number: 10339003
    Abstract: A method by a dispersed storage (DS) processing unit of a dispersed storage network (DSN) begins by sending a set of data access requests regarding a data access transaction to a set of storage units of the DSN. The method continues by receiving from each of at least some storage units, a storage-revision indicator which includes a content-revision field, a delete-counter field, and a contest-counter field. The method continues by generating an anticipated storage-revision indicator based on a current revision level of the set of encoded data slices and based on a data access type of the data access transaction. The method continues by comparing the anticipated storage-revision indicator with the storage-revision indicators. When a threshold number of the storage-revision indicators received from the at least some storage units substantially match the anticipated storage-revision indicator, the method continues by executing the data access transaction.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 2, 2019
    Inventors: Greg R. Dhuse, Ravi V. Khadiwala
  • Patent number: 10333557
    Abstract: According to one embodiment, a memory system includes a first volatile memory, a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of chips. The controller generates a second error correcting code using data stored in the first volatile memory. The second error correcting code is a code for correcting data which cannot be corrected included in a first data group using a first error correcting code. The controller releases an area of the first volatile memory corresponding to the first data group written in the nonvolatile memory, before completion of writing of all of the data which are stored in the first volatile memory and includes in a codeword of the second error correcting code to the nonvolatile memory.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 25, 2019
    Inventors: Erika Kaku, Yoshihisa Kojima
  • Patent number: 10324648
    Abstract: Systems and methods are disclosed for wear-based access optimization. An apparatus may comprise a circuit configured to perform a data access operation at a target location of a memory, and determine a wear value of the target location. The circuit may compare the wear value to global wear value of other locations of the drive, and adjust data access parameters for the target location based on the comparison.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: June 18, 2019
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Antoine Khoueir, Ara Patapoutian
  • Patent number: 10317462
    Abstract: An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading. The wide-range test clock signal is generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: June 11, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Tzu-Heng Huang
  • Patent number: 10320424
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 11, 2019
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 10319447
    Abstract: A storage device includes a nonvolatile memory device and a controller. A nonvolatile memory device includes a plurality of memory blocks. Each of the plurality of memory blocks is divided into a plurality of zones and is formed on a substrate. Each of the plurality of zones comprises one or more word lines. A controller performs a reliability verification read operation on a first zone of the plurality of zones of a memory block selected from the plurality of memory blocks if a number of read operations performed on the first zone reaches a first threshold value and performs the reliability verification read operation on a second zone of the plurality of zones of the selected memory block if a number of read operations performed on the second zone reaches a second threshold value.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 11, 2019
    Inventors: Young-Seop Shim, Jaehong Kim
  • Patent number: 10317464
    Abstract: An example test circuit for an integrated circuit (IC) having a plurality of scan chains includes: a first circuit and a second circuit; and a scan chain router coupled between the first circuit and the plurality of scan chains and coupled between the second circuit and the plurality of scan chains, the scan chain router responsive to an enable signal to: (1) couple the first circuit to each of the plurality of scan chains; or (2) couple the second circuit to one or more concatenated scan chains, where each concatenated scan chain includes a concatenation of two or more of the plurality of scan chains.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventor: Partho Tapan Chaudhuri
  • Patent number: 10313062
    Abstract: Provided in one disclosure of the present specification is a method for transmitting a hybrid automatic repeat request (HARQ) acknowledgement (ACK)/negative-acknowledgement (NACK) for downlink data, when more than five cells are used according to carrier aggregation (CA) by a user equipment (UE).
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: June 4, 2019
    Inventors: Daesung Hwang, Suckchel Yang, Seungmin Lee, Hanjun Park
  • Patent number: 10312937
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to early termination techniques for low-density parity-check (LDPC) decoder architecture.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: June 4, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Vincent Loncke, Yi Cao, Girish Varatkar
  • Patent number: 10303364
    Abstract: Techniques are described for decoding a first message. In one example, the techniques include obtaining a second message comprising reliability information corresponding to each bit in the first message, performing a soft decision decoding procedure on the second message to generate a decoded codeword, wherein the soft decision decoding procedure comprises a joint decoding and miscorrection avoidance procedure, and outputting the decoded codeword.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: May 28, 2019
    Assignee: SK Hynix Inc.
    Inventors: Aman Bhatia, Yi-Min Lin, Naveen Kumar, Fan Zhang
  • Patent number: 10305633
    Abstract: The present disclosure provides techniques for performing bit-level interleaving for orthogonal frequency-divisional multiplexing (OFDM) symbols across a plurality of code blocks. In some aspects, a transmitting device may dynamically switch between bit-level interleaving and tone-level interleaving for each OFDM symbol based on factors such as number of bits that are carried in each tone, size of each code block, the processing time requirements of the transmitting device and/or the receiving device, or the transmitting device preference.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 28, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Alexandros Manolakos, Hari Sankar, Peter Ang, Krishna Mukkavilli, Joseph Binamira Soriaga, Tingfang Ji, Alexei Gorokhov, Peter Gaal
  • Patent number: 10305629
    Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: May 28, 2019
    Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
  • Patent number: 10304559
    Abstract: A device is disclosed that includes a data write engine configured to store data into a block of a memory. The device also includes a post-write read engine configured to adjust a read voltage responsive to an output of the temperature sensor and to read stored data from the block based on the adjusted read voltage to verify integrity of the data. The device also includes a block manager configured to initiate a corrective operation responsive to an error characteristic of the data read from the block.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 28, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Himanshu Hemant Naik, Biswajit Ray, Mohan Vamsi Dunga, Changyuan Chen
  • Patent number: 10305516
    Abstract: Embodiments relate to a system with multiple erasure codes, and selecting and encoding for a write file with one of the codes to mitigate costs associated with storage recovery. The codes include a fast recovery code for frequently accessed data and a higher storage efficiency code for less frequently accessed data. State data is tracked to ascertain frequency of access to the file. One of the erasure codes is dynamically selected based on the tracked data, with the focus of the code select to lower recovery costs, and the data is encoded with the selected erasure code. Accordingly, the original coding of the write file is subject to change based on the tracked state data.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, James L. Hafner, David A. Pease, Mohit Saxena, Mingyuan Xia
  • Patent number: 10291263
    Abstract: A method for identifying log likelihood ratio (LLR) values includes programming codewords into nonvolatile memory devices in response to receiving host-requested write instructions and performing background reads of the programmed codewords in a block at a default threshold voltage, at one or more threshold voltage offset that is less than the default threshold voltage and at one or more threshold voltage offset that is greater than the default threshold voltage. One of the background reads is decoded to identify the stored codeword(s) and a set of LLR values is identified using the stored read results and the identified codeword(s). The process of performing background reads, storing, decoding and identifying is repeated to identify a set of LLR values for each block and further to identify updated sets of LLR values. Host-requested reads are performed and are decoded using LLR values from the updated set of LLR values corresponding to the block that was read.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: May 14, 2019
    Assignee: IP GEM GROUP, LLC
    Inventors: Alessia Marelli, Rino Micheloni
  • Patent number: 10288682
    Abstract: An electronic device having a functional portion and a test portion. The test portion includes a boundary scan register formed by a plurality of test cells arranged in the body according to a register sequence, where first test cells are configured to form a serial-to-parallel converter and second test cells are configured to form a parallel-to-serial converter. The test cells are each coupled to a respective data access pin of the device and to a respective input/output point of the functional part and have a first test input and a test output. The boundary scan register defines two test half-paths formed, respectively, by the first test cells and by the second test cells. The first test cells are directly coupled according to a first sub-sequence, and the second test cells are directly coupled according to a second sub-sequence.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: May 14, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani