Patents Examined by Fritz Alphonse
  • Patent number: 10067826
    Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: September 4, 2018
    Assignee: Infineon Technologies AG
    Inventors: Thomas Rabenalt, Ulrich Backhausen, Thomas Kern, Michael Goessel
  • Patent number: 10069833
    Abstract: A computer security method including detecting access, by a computer in a first computer network, to a computer-readable document, determining whether the computer-readable document was retrieved from a second computer network, identifying a reference, associated with the computer-readable document, to a resource at a location within the first computer network, and preventing access by the computer to the resource at the location within the first computer network responsive to determining that the computer-readable document was retrieved from the second computer network.
    Type: Grant
    Filed: November 29, 2015
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shmuel Regev, Amit Klein
  • Patent number: 10062446
    Abstract: A circuit architecture for operating error-correction code (ECC) in a memory apparatus includes a control circuit and an ECC circuit. The ECC circuit is coupled with the control circuit. The control circuit receives a first data of a set of bits to invert the first data as an inverted data. The ECC circuit receives the inverted data for encryption or decryption and outputs an ECC-processed data. The control circuit inverts the ECC-processed data as a second data.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 28, 2018
    Assignee: eMemory Technology Inc.
    Inventor: Po-Hao Huang
  • Patent number: 10061649
    Abstract: A method for execution by a dispersed storage and task (DST) processing unit includes generating a plurality of encoded slices of a data object by performing an encoding function on the data object. Slice stream data is generated that includes a plurality of mutually exclusive slice subsets of the plurality of encoded slices, where each of the plurality of slice subsets is assigned to a corresponding one of a plurality of storage units, and where the encoded slices of each slice subset correspond to contiguous segments of the data object. A plurality of write requests that include the plurality of encoded slices are generated, each for transmission to the corresponding one of the plurality of storage units indicated by the slice stream data via a network.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: August 28, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew D. Baptist, Greg R. Dhuse, Ethan S. Wozniak
  • Patent number: 10056921
    Abstract: A memory system is disclosed. The memory system includes: a memory; a first ECC circuit used to encode information bits of a first length into a codeword of a first ECC scheme, and to decode a codeword of the first ECC scheme read from the memory into decoded information bits of the first length; a second ECC circuit used to encode information bits of a second length into a codeword of a second ECC scheme, and to decode a codeword of the second ECC scheme read from the memory into decoded information bits of the second length; and a control circuit used to combine a plurality sets of the decoded information bits of the first length into the information bits of the second length, and to separate the decoded information bits of the second length into a plurality sets of the information bits of the first length.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Lien Linus Lu, Yu-Der Chih
  • Patent number: 10055282
    Abstract: Systems, methods, and other embodiments associated with cyclic redundancy checking for wide data busses are described. According to one embodiment, a method comprises, in response to detecting a data block on a data bus, identifying a data lane of the data bus on which the data block begins and initializing a starting processing unit of a series of processing units. The starting processing unit corresponds with the identified data lane by issuing a mask input to prior processing units that are ahead of the starting processing unit within the series. Issuing the mask input causes the prior processing units to feed a seed value to the starting processing unit. A cyclic redundancy check value is generated for the data block by initiating the generating from the starting processing unit and iteratively cycling through the series of processing units until the block of data is completed.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: August 21, 2018
    Assignee: Marvell International Ltd.
    Inventors: Jun Zhu, Akshay Chandra
  • Patent number: 10057016
    Abstract: An efficient retransmission mechanism for use in consideration of uncertainty of resource availability on unlicensed carriers in a Licensed-Assisted Access scenario. Particularly, there is provided a method for data transmission at a first communications device operable in both a licensed spectrum and an unlicensed spectrum. The method comprises initially transmitting a data block on an unlicensed carrier of the unlicensed spectrum to a second communications device operable in both the licensed spectrum and the unlicensed spectrum and retransmitting the data block to the second communications device in response to receiving a negative acknowledgement from the second communications device. The method also comprises abandoning the retransmission under a predetermined condition associated with the unlicensed carrier. Correspondingly, there is also provided an apparatus for data transmission at a communications device operable in both a licensed spectrum and an unlicensed spectrum.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: August 21, 2018
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Qianxi Lu, Rui Fan, Xinghua Song, Mattias Tan Bergström
  • Patent number: 10055284
    Abstract: Systems, methods, and computer programs are disclosed for providing error detection or correction with flash cell mapping. One embodiment is a method comprising generating raw page data for a physical page in a main array of a flash memory device. The raw page data comprises less than a capacity of the physical page generated using a non-power-of-two flash cell mapping. One or more parity bits are generated for the raw page data using an error detection or correction scheme. The method stores the raw page data and the one or more parity bits in the physical page in the main array.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 21, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Richard Alan Stewart, Dexter Tamio Chun
  • Patent number: 10055291
    Abstract: A method for execution by a storage unit of a dispersed storage network, the method comprises transitioning storage of one or more groups of encoded data slices from storage based on a previous version of a distributed agreement protocol to storage based on a new version of the distributed agreement protocol. While transitioning storage of the one or more groups of encoded data slices, receiving, from a requesting computing device, a data access request regarding an encoded data slice of the one or more groups of encoded data slices. Determining whether the encoded data slice has been transferred as a result of the transitioning. When the storage unit is currently storing the encoded data slice, processing the data access request. When the storage unit is not currently storing the encoded data slice, functioning as a proxy for the requesting computing device to fulfill the data access request.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew D. Baptist, Ravi V. Khadiwala, Manish Motwani, Jason K. Resch
  • Patent number: 10057309
    Abstract: Examples discussed herein relate to a system including a first data processing system and a second data processing system. The first data processing system can be configured to receive a first partial media stream of a media stream split into at least the first partial media stream and a second partial media stream and send the first partial media stream to a device. The second data processing system can be configured to receive the second partial media stream and send the second partial media stream to the device.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 21, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Danny Levin, Bradford R. Clark, Amer Hassan
  • Patent number: 10048317
    Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: August 14, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain Clerc, Gilles Gasiot
  • Patent number: 10044371
    Abstract: Systems and methods which implement repair bandwidth control techniques, such as may provide a feedback control structure for regulating repair bandwidth in the storage system. Embodiments control a source object repair rate in a storage system by analyzing source objects represented in a repair queue to determine repair rate metrics for the source objects and determining a repair rate based on the repair rate metrics to provide a determined level of recovery of source data stored as by the source objects and to provide a determined level of repair efficiency in the storage system. For example, embodiments may determine a per storage object repair rate (e.g., a repair rate preference for each of a plurality of source objects) and select a particular repair rate (e.g., a maximum repair rate) for use by a repair policy. Thereafter, the repair policy of embodiments may implement repair of one or more source objects in accordance with the repair rate.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: August 7, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Michael George Luby
  • Patent number: 10033408
    Abstract: An iterative decoder is controlled to iteratively decode a block by performing one or more decoding iterations for the block. The iterative decoder uses a parity-check matrix and can be configured to process that parity-check matrix for parallel, sequential or a combination of parallel and sequential (“hybrid”) parity constraint updates.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: July 24, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ara Patapoutian, Bruce Buch, Rose Shao
  • Patent number: 10026501
    Abstract: A method for operating a data storage device includes obtaining test data from a target region of a memory block by applying a test bias simultaneously to all word lines of the memory block; and estimating a state of the memory block based on the test data.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: July 17, 2018
    Assignee: SK Hynix Inc.
    Inventor: Dae Seok Shin
  • Patent number: 10020065
    Abstract: A device includes a non-volatile solid-state memory array comprising a plurality of blocks, each of the plurality of blocks configured to store data in a single-bit per cell mode or a multiple-bit per cell mode, and a controller. The controller is configured to receive write data from a host device, program the write data to a first block of the plurality of blocks of the memory array using the single-bit per cell mode, and perform a data consolidation operation on the first block at least in part by programming at least a portion of the write data together with data stored in a separate second block of the memory array to a third block of the memory array using the multiple-bit per cell mode.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: July 10, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: David S. Seekins, Dennis M. Rolland
  • Patent number: 10013308
    Abstract: Provided are a semiconductor device including an error correction code circuit and a driving method thereof. The semiconductor device includes a plurality of normal mats including a plurality of memory cells and connected to data lines, a plurality of dummy mats arranged in specific areas of the plurality of normal mats and inputting/outputting parity bits through parity lines of a specific circuit, a plurality of free ECC (Error Correction Code) calculation circuits that perform ECC calculation corresponding to data applied through the data lines and the parity lines, and a main ECC calculation circuit that combines data applied from the plurality of free ECC calculation circuits with one another and performs ECC calculation.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: July 3, 2018
    Assignee: SK hynix Inc.
    Inventors: Min Su Park, Jin Hee Cho
  • Patent number: 10014881
    Abstract: Embodiments relate to dynamically selecting an erasure code. State data is tracked to ascertain frequency of file access. One of at least two erasure codes are selected based on the tracked state data in order to lower data recovery cost. The erasure code may be selected as either a product code or a local reconstruction code. Each erasure code includes a mode that is either a fast code or a compact code. The fast code features a low recovery cost and the compact code features a low storage overhead for less frequently accessed data. Data is encoded with one of the selected erasure codes and one of the modes of the selected erasure code. Data blocks are dynamically converted between the fast and compact codes of the selected erasure code responsive to a workload change.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, James L. Hafner, David A. Pease, Mohit Saxena, Mingyuan Xia
  • Patent number: 10014981
    Abstract: The present invention discloses a transmission method and device based on a management data input/output multi-source agreement. The method includes that: at least one frame is sent, and a host indicates, according to opcodes carried by the at least one frame, to perform a data reading operation or a continuous data reading operation or a data writing operation on an optical module; the at least one frame is used, during checking, for respectively calculating check values at the host and the optical module; it is determined, according to a result of comparison between the check values, whether the check values are correct, and it is decided whether it is needed to repeat the data reading operation or the continuous data reading operation or the data writing operation.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: July 3, 2018
    Assignee: ZTE CORPORATION
    Inventor: Yijun Xu
  • Patent number: 9991008
    Abstract: Systems and methods for analyzing and reducing the failure rates due to soft errors in a design are provided. One such method involves analyzing the design by reading the design from a register-transfer-level language description or a netlist, manufacturing process soft error information, library information and timing constraints for the design to generate the failure in time (FIT) rate for the modules in the design.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: June 5, 2018
    Assignee: Austemper Design Systems Inc.
    Inventor: Sanjay Pillay
  • Patent number: 9990160
    Abstract: One embodiment relates to a memory structure that includes a bank group and a port emulation circuit module. The bank group includes a plurality of memory banks, each memory bank having one read port and one write port. The port emulation circuit module provides a group read/write port and a group read port for the bank group. Another embodiment relates to a port emulation circuit module. The port emulation circuit module includes a port emulation control circuit that receives control signals including a first address for a group read/write port and a second address for a group read port, a first data path circuit for the group read/write port, and a second data path circuit for the group read port, wherein the second data path circuit outputs a second read data. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: June 5, 2018
    Assignee: Altera Corporation
    Inventor: Chee Hak Teh