Patents Examined by Fritz Alphonse
  • Patent number: 9838045
    Abstract: A system and method for storing compressed data in a memory system includes identifying user data to be compressed and compressing pages of user data to form data extents that are less than or equal to the uncompressed data. A plurality of compressed pages are combined to a least fill a page of the memory. The data may be stored as sectors of a page, where each sector includes a CRC or error correcting code for the compressed data of that sector. The stored data may also include error correcting code data for the uncompressed page and error correcting code for the compressed page. When data is read in response to a user request, the sector data is validated using the CRC prior to selecting the data from the read sectors for decompression, and the error correcting code for the uncompressed page may be used to validate the decompressed data.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: December 5, 2017
    Inventor: Jon C. R. Bennett
  • Patent number: 9836239
    Abstract: A recording device includes a plurality of storage modules and a recording controller. With respect to a writing request, the recording controller generates parity data and writes data in the respective plurality of modules by dividing the data. When an error is detected with respect to a reading request, data of the error is restored from data and the parity data read from other recording modules. With respect to an initialization request of the storage module, the storage module to be initialized is specified from the plurality of storage modules, and an address conversion table is initialized. Moreover, identification information for identifying the initialized storage module is held. With respect to a request for cancelling the table initialization request of the storage module, reading of data from the storage module corresponding to the held identification information is processed as an error.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: December 5, 2017
    Inventors: Hideaki Yamashita, Takeshi Otsuka
  • Patent number: 9835682
    Abstract: A debugging system includes an embedded device and a terminal computer. The embedded device includes a memory unit, and the memory unit includes a first buffer, the embedded device is configured for executing at least one instruction to generate at least one real-time debugging information, and writing the real-time debugging information into the first buffer. The terminal computer is connected to an in-circuit emulator (ICE) via a first interface, and the ICE is connected to the embedded device via a second interface. The terminal computer uses polling to read the real-time debugging information stored in the first buffer via the ICE, and deletes the real-time debugging information stored in the first buffer afterwards.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: December 5, 2017
    Assignee: Nuvoton Technology Corporation
    Inventors: Yung-Ching Hsu, Hsin-Chou Lee
  • Patent number: 9830218
    Abstract: The exemplary embodiments of the invention relates to fault tolerance of a cache memory which recovers an error occurred in the cache memory or reports an error. A cache memory may include a first layer cache configured to store data requested from a processor, together with a tag related to the data and parity check bits for detecting data error and tag error; a second layer cache configured to store data requested from the first layer cache, together with parity check bits and an error correction code(ECC) bit for detecting data error and tag error; and a fault tolerance unit configured to generate an error signal indicating whether the data error or tag error occurred in at least one of the first layer cache and the second layer cache is recoverable.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: November 28, 2017
    Inventors: Jin-Ho Han, Young-Su Kwon
  • Patent number: 9823969
    Abstract: Systems and techniques for managing data storage are disclosed. In some aspects, a front-end node responds to a request to write an object by dividing the object into multiple source data segments. The front-end node generates redundancy data for the multiple source data segments using a rateless erasure encoding. The front-end node associates a respective subset of the redundancy data with each of the multiple source data segments, wherein each subset of redundancy data and associated source data segment form an encoded segment. The rateless erasure encoding further includes defining multiple segment-level fragments within each of the encoded segments. The front-end node transmits each of the encoded segments to a selected one of multiple storage nodes, wherein each of the selected storage nodes are selected based on a determined storage layout of the encoded segments across the multiple storage nodes.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: November 21, 2017
    Assignee: NetApp, Inc.
    Inventors: David Anthony Slik, Barry Patrick Benight
  • Patent number: 9823960
    Abstract: A cyclic redundancy check (CRC) device configured to support parallel calculation of a CRC value for a data frame comprises a plurality of CRC processing units each configured to accept one of a plurality of data segments of the data frame of a variable size that can be unknown to the CRC device beforehand and generate one of plurality of partial CRC values in parallel with rest of the CRC processing units over multiple clock cycles/iterations. The CRC device further comprises an integration component configured to integrate the plurality of partial CRC values from the plurality of CRC processing units into one final CRC value for the data frame, wherein the final CRC value is attached to the data frame for error checking during storage or transmission of the data frame.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: November 21, 2017
    Assignee: CAVIUM, INC.
    Inventor: Weihuang Wang
  • Patent number: 9826038
    Abstract: A method begins by a computing device of a dispersed storage network (DSN) sending, to a set of storage units of the DSN, a set of write requests regarding a set of encoded data slices, where each write request includes a write set information table that includes a listing of which storage unit of the set of storage units is being sent which encoded data slice of the set of encoded data slices for storage. The method continues with at least some of the storage units receiving write requests of the set of write requests. The method continues with one of the storage units interpreting the write set information table to determine that a particular encoded data slice assigned to a particular storage unit should be stored by a different storage unit and facilitating storing of the particular encoded data slice in the different storage unit.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: November 21, 2017
    Inventors: Jason K. Resch, Wesley Leggette, Greg Dhuse
  • Patent number: 9825652
    Abstract: Techniques described and suggested herein include systems and methods for minimizing inter-facility data transfer during retrieval of data archives stored on data storage systems using redundancy coding techniques. For example, redundancy coded shards, which may include identity shards that contain unencoded original data of archives, may be configured such that a variable number of the shards can be leveraged to meet performance requirements or time-to-retrieval limitations for retrieval requests associated with the archives stored and/or encoded therein. Under some circumstances, implementing systems may monitor throughput rates, capabilities, and burdens, so as to preferentially retrieve data such that the identity shards are favored and fewer hosting data storage facilities are used for a given retrieval.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: November 21, 2017
    Inventor: Colin Laird Lazier
  • Patent number: 9823304
    Abstract: An electronic device having a functional portion and a test portion. The test portion includes a boundary scan register formed by a plurality of test cells arranged in the body according to a register sequence, where first test cells are configured to form a serial-to-parallel converter and second test cells are configured to form a parallel-to-serial converter. The test cells are each coupled to a respective data access pin of the device and to a respective input/output point of the functional part and have a first test input and a test output. The boundary scan register defines two test half-paths formed, respectively, by the first test cells and by the second test cells. The first test cells are directly coupled according to a first sub-sequence, and the second test cells are directly coupled according to a second sub-sequence.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: November 21, 2017
    Inventor: Alberto Pagani
  • Patent number: 9819364
    Abstract: The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as a long term evolution (LTE). A method for transmitting a signal in a signal transmitting apparatus in a communication system supporting a bit-interleaved coded modulation with iterative decoding (BICM-ID) scheme is provided. The method includes performing an outer encoding operation; performing an interleaving operation on the outer code corresponding to an interleaving scheme which is based on a preset generation matrix to generate an interleaved signal; performing an inner encoding operation; performing a modulating operation; and transmitting the modulated signal, wherein the generation matrix is generated by applying at least one of a preset column permutation rule and a preset row permutation rule to a generation matrix for a quasi-cyclic (QC) interleaver.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: November 14, 2017
    Inventors: Jeong-Seok Ha, Woo-Myoung Park, Sang-Ha Lee, Jae-Yoon Lee
  • Patent number: 9804919
    Abstract: Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for recovering data where synchronization information is not detected.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: October 31, 2017
    Inventors: Yuqing Yang, Shaohua Yang, Xuebin Wu, Qi Zuo
  • Patent number: 9798614
    Abstract: An operating method of a controller includes generating error reliability of data based on reliability information of one or more error-corrected bits of the data, wherein the data is read out from a semiconductor memory device and a hard decision ECC decoding to the data through a BCH code is determined as successful; and determining miscorrection of the data based on the error reliability.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: October 24, 2017
    Assignee: SK Hynix Inc.
    Inventor: Do-Hun Kim
  • Patent number: 9793923
    Abstract: Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: October 17, 2017
    Inventors: Yaoyu Tao, Joyce Kwong
  • Patent number: 9787436
    Abstract: Routing on Wi-Fi or similar home networks is improved though the use of a proxy service located on the home network. If wireless networking issues arise, the proxy can adapt delivery of digital content in an intelligent manner. If client communications are becoming increasingly unreliable, for example, the proxy can respond with additional error correction and/or packet retransmissions, in contrast to conventional TCP techniques for responding to network issues. Other corrections and features may be built into the proxy protocol as desired.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: October 10, 2017
    Assignee: EchoStar Technologies L.L.C.
    Inventors: Robert Drew Major, Darren Major
  • Patent number: 9785570
    Abstract: An embodiment includes a system, comprising: an Error Correcting Code (ECC) memory comprising a plurality of memory locations, each memory location corresponding to a device address of the ECC memory; a system management bus (SMB); a baseboard management controller (BMC) coupled to the ECC memory through the SMB; and an operating system comprising a driver module coupled to the BMC through the SMB, the driver module being configured to receive through the Memory device address information associated with the ECC memory and to convert the device address information into physical address information independent of an ECC memory controller.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: October 10, 2017
    Inventors: Chaohong Hu, Hongzhong Zheng, Dimin Niu
  • Patent number: 9787332
    Abstract: A compression engine may be designed for more efficient error checking of a compressed stream, to include adaptation of a heterogeneous design that includes interleaved hardware and software stages of compression and decompression. An output of a string matcher may be reversed to generate a bit stream, which is then compared with an input stream to the compression engine as a first error check. A final compressed output of the compression engine may be partially decompressed to reverse entropy code encoding of an entropy code encoder. The partially decompressed output may be compared with an output of an entropy code generator to perform a second error check. Finding an error at the first error check greatly reduces the latency of generating a fault or exception, as does performing computing-intensive aspects of the compression and decompression with software instead of specialized hardware.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal, Laurent Coquerel
  • Patent number: 9785383
    Abstract: According to one embodiment, a memory controller of a memory system includes a command issuing unit, a decoder, a counter, and a statistical processor. The command issuing unit issues a first command for single read of first data from a nonvolatile memory. The decoder performs first error correction on the read first data. The counter counts a number of times of multiple reads. The statistical processor performs statistical processing of results of the multiple reads, and outputs second data obtained by the statistical processing. When the decoder is unable to perform the first error correction on the read first data, the command issuing unit issues a second command for multiple reads of the first data.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: October 10, 2017
    Inventors: Takehiko Amaki, Riki Suzuki, Toshikatsu Hida
  • Patent number: 9778981
    Abstract: A microcontroller includes a nonvolatile memory. The microcontroller executes an ECC error detection to detect an ECC error during a main process, which accesses the nonvolatile memory, and an interrupt process when the ECC error occurs. The interrupt process executes a change process that specifies an instruction causing the ECC error, which is detected by the ECC error detection, and changes a program counter to skip the specified instruction and to execute a next instruction. The microcontroller executes an abnormality value storage process that stores an abnormality value in a storage destination of a read value, and the read value is read in the main process after the change process.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: October 3, 2017
    Inventors: Hironori Shirai, Takaomi Kajikawa
  • Patent number: 9778861
    Abstract: A method for controlling flash memory is described. The method includes selecting a new forward error correction (FEC) parameter set that provides more redundancy than a current FEC parameter set. The method also includes coding source information bits, using the new FEC parameter set, during write operations to a first corrupted page in the flash memory. The method further includes mapping the first corrupted page and at least one additional corrupted page in the flash memory to a single logical page with an expected page size.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: October 3, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Yinian Mao
  • Patent number: 9766859
    Abstract: Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: September 19, 2017
    Inventors: James R. Cuffney, John G. Rell, Jr., Eric M. Schwarz, Patrick M. West, Jr.