Patents Examined by Fritz Alphonse
  • Patent number: 10734058
    Abstract: A memory device includes an error correction code (ECC) block suitable for performing an ECC operation, and generating a flag signal when an error is detected and corrected through the ECC operation in data read from a memory cell array, and a refresh control block suitable for comparing an active row address with a target address in response to the flag signal, and refreshing data of a neighboring address of the target address based on a comparison result.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Seok-Bo Shim, Sang-Ho Lee, Seok-Cheol Yoon, Yun-Young Lee
  • Patent number: 10732862
    Abstract: A method of storing data includes receiving general purpose (GP) data and special Error Tolerant or Streaming (ETS) data, storing the GP data using a data storage method, and storing the ETS data using a different data storage method which affects the access rate, resilience to errors, data integrity, storage density, or storage capacity. The storage medium, which can include a disk drive, flash memory, or holographic memory, is utilized differently depending on the required Quality of Service in aspects including block size, storage of error correction codes, utilization of error correction codes, storage area density, physical format pattern, storage verification, or reaction to failed storage verification. For disk drives these differences include spacing between tracks; overlap between tracks; spiral track formatting; concentric track formatting, and size of blocks, and for flash memories these differences include levels per cell and number of cells.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: August 4, 2020
    Inventors: Rod Brittner, Ronald G. Benson
  • Patent number: 10725861
    Abstract: System and techniques for error correction code (ECC) memory security are described herein. A write request that includes data is received. An integrity check value (ICV) is computed for the data. Then, the write request is performed, including writing a representation of the data to a data area in memory and writing the ICV into an ECC area in memory. Here, the data area is addressable by a host and the ECC area corresponds to the data area via hardware of the memory.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Anatoli Bolotov, Mikhail Grinchuk, Rajat Agarwal
  • Patent number: 10725912
    Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Andrew M. Kowles
  • Patent number: 10719395
    Abstract: According to one embodiment, a memory system includes an error mitigation encoder that executes error mitigation coding on write data to be stored in a processing target page of a non-volatile memory, a memory interface that writes the write data which has undergone the error mitigation coding in the processing target page of the non-volatile memory and reads the write data which has undergone the error mitigation coding from the processing target page as read data, an error mitigation decoder that performs error mitigation decoding on the read data read from the processing target page of the non-volatile memory, and an error mitigation coding rate deciding unit that decides an error mitigation coding rate of the error mitigation encoder and the error mitigation decoder on the basis of at least one of information indicating the processing target page and information indicating a device characteristic of the processing target page.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: July 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tokumasa Hara, Kejen Lin, Sho Kodama, Keiri Nakanishi, Kohei Oikawa
  • Patent number: 10719392
    Abstract: Systems and methods are disclosed for error recovery in a digital data channel. In an error recovery approach when the hardware fails to recover a sector, the sample for that sector can be saved along with a metric measure that indicates the quality of the sample. This process can begin from a first on-the-fly receiving and decoding of data. During each step of error recovery, a retry attempt may either use samples obtained during a new decoding attempt or may use a sample, or a combination of samples, having the best metric from an earlier attempt, or a combination of earlier attempts, to perform the recovery during a current retry recovery attempt.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 21, 2020
    Assignee: Seagate Technology LLC
    Inventors: Deepak Sridhara, Ara Patapoutian
  • Patent number: 10713115
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: July 14, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Patent number: 10706948
    Abstract: A method for multi-level memory safety for a sensor integrated circuit can include loading a blocking bit into a volatile memory from a non-volatile memory and providing the blocking bit to a gating circuit from the volatile memory. Further, the method may include the gating circuit determining whether to provide a default value to a functional logic based upon the provided blocking bit.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: July 7, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Nicolas Rafael Biberidis, Octavio H. Alpago, Nicolas Rigoni
  • Patent number: 10700709
    Abstract: Apparatus and method relates generally to data processing kernel. In such an apparatus, a datapath pipeline is configured to process datasets interlaced with respect to one another for multiple passes through a loop with conditional or data dependent decision points. A queue manager is configured with control circuitry sets to provide an instruction interface to the datapath pipeline. Each of the control circuitry sets includes: a first buffer and a second buffer each configured to buffer tokens for correspondence with the datasets. Each of the control circuitry sets further includes: an arbiter configured to decouple the conditional or data dependent decision points from the datapath pipeline to selectively provide access of the first buffer or the second buffer to the datapath functions. Memory is configured to provide access to and storage of the datasets to the datapath pipeline.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 30, 2020
    Assignee: XILINX, INC.
    Inventor: Gordon I. Old
  • Patent number: 10698778
    Abstract: A dispersed storage network (DSN) includes multiple storage units. A processing unit included in the DSN issues an access request to one of the storage units, and identifies the storage unit as a failing storage unit based, at least in part, on a rate of growth of a network queue associated with the storage unit. the processing unit then issues an error indicator to a recovery unit for further action.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: June 30, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Kumar Abhijeet, Andrew D. Baptist, Ilir Iljazi, Gregory A. Papadopoulos, Jason K. Resch
  • Patent number: 10691569
    Abstract: A system for testing a data storage device includes the data storage device, an electronic device and a computer device. The electronic device includes a host device coupled to the data storage device and communicating with the data storage device via an interface logic. The computer device is coupled to the electronic device and is configured to issue a plurality of commands to test the data storage device in a test procedure. When the electronic device has been successfully started up, the computer device issues a first command to the electronic device to trigger the electronic device to enter a hibernate mode. After waiting for a first predetermined period of time, the computer device issues a second command to the electronic device, so as to wake up the electronic device.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 23, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Po-Yi Shih
  • Patent number: 10691539
    Abstract: A controller may detect unreliable bits of data, memory cells, or bit lines during an error correction process of a read operation based on an error correction code used to generate parity bits for the data. In some embodiments, the controller may use the error correction code to determine a distribution of unsatisfied checks. Based on the distribution, the controller may detect group(s) of bits that more closely resemble a defective group of bits rather than a non-defective group of bits. Based on the detection, the controller may set reliability metrics to values that indicate low levels or reliability, which in turn may increase the probability of successfully correcting the errors and reduce the amount of work the controller needs to do in order to complete the error correction process.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 23, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ran Zamir, Eran Sharon, Idan Alrod
  • Patent number: 10693590
    Abstract: Embodiments of this application provide a method for coding in a wireless communication network. A communication device interleave a first bit sequence to obtain a first interleaved sequence having sequence number starting with a sequence number of 0, wherein the first bit sequence comprises bits for indicating timing, wherein the bits for indicating timing comprises a set of bits for indicating synchronization signal block index (SSBI); wherein the set of bits for indicating SSBI are placed in positions indicated by sequence numbers of 2, 3 and 5 in the first interleaved sequence. The devices add d first CRC bits on the first interleaved sequence to obtain a second bit sequence, interleave on the second bit sequence according to an interleave pattern to obtain a second interleaved sequence, and polar encode the second interleaved sequence to obtain the encoded sequence.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: June 23, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hejia Luo, Yinggang Du, Rong Li, Lingchen Huang, Ying Chen
  • Patent number: 10686469
    Abstract: Size ambiguity and false alarm rate reduction for polar codes. A user equipment (UE) may determine a decoding candidate bit sequence for a polar-encoded codeword having a codeword size based on a decoding hypothesis for control information having a particular bit length of multiple different bit lengths for the codeword size. The UE may calculate an error detection code (EDC) value for a payload portion of the decoding candidate bit sequence using an EDC algorithm, and may initialize an EDC variable state with at least one non-zero bit value. Scrambling or interleaving of bits may also be performed prior to, or after, polar encoding and may depend on the bit length. In examples, information bits may be bit-reversed prior to generating an EDC value. In examples, the encoded bits may include multiple EDC values to assist the UE in performing early termination and to reduce a false alarm rate.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: June 16, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Huang Lou, Jing Jiang, Enoch Shiao-Kuang Lu, Gabi Sarkis, Yang Yang, Hari Sankar
  • Patent number: 10684326
    Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: June 16, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain Clerc, Gilles Gasiot
  • Patent number: 10686853
    Abstract: Online content is served to participant devices using two or more systems. The content served by each system is not the same. Rather, the content streams coming from each system is a partial or lower-quality version of the original high-quality version of the content stream. A single one of the partial data streams can be used by the participant device to output a lower-quality version of the original content stream to the user. Alternately, the received partial content streams can be combined to output, to the user, a high-quality version of the original content stream.
    Type: Grant
    Filed: August 19, 2018
    Date of Patent: June 16, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Danny Levin, Bradford R. Clark, Amer Hassan
  • Patent number: 10680656
    Abstract: A memory controller includes a command input unit suitable for receiving a write command, a read command, and a send command, a command counting unit suitable for performing a counting operation in response to the write command to produce a counted data, a first Error Correction Code (ECC) encoding unit suitable for performing a first ECC encoding onto a data that is read from a memory device in response to the read command to produce a first ECC encoded data, a second ECC encoding unit suitable for performing a second ECC encoding onto the counted data in response to the send command to produce a second ECC encoded data, and a data output unit suitable for combining the first ECC encoded data and the second ECC encoded data to output a read data.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Young-Ook Song, Sang-Gu Jo, In-Hwa Jung
  • Patent number: 10678719
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 9, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Kenneth L. Wright, John Eric Linstadt, Craig Hampel
  • Patent number: 10673569
    Abstract: Methods and arrangements for managing a retransmission on a Random Access CHannel, “RACH”, in a wireless communication network (100). A device (600; 120) performs (404; 502) the retransmission on the RACH, wherein the retransmission is based on a coverage class associated with the device (600; 120). Basing the retransmission on the coverage class e.g. enables reduction of retransmission collisions when the wireless communication network (100) operates as in Extended Coverage GSM, “EC-GSM”.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: June 2, 2020
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Björn Hofström, John Walter Diachina, Nicklas Johansson, Claes-Göran Persson
  • Patent number: 10666381
    Abstract: Systems, methods, and software technology for partitioning media streams is disclosed herein. In an implementation, an application partitions an encoded media stream into multiple sub-streams having different code rates relative to each other. The sub-streams may then be transmitted to different wireless access points. A change in a monitored performance of at least one of the wireless access points may drive a modification to the partitioning of the media stream such that the code rates change relative to each other.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 26, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Amer Hassan