Patents Examined by Fritz Alphonse
  • Patent number: 9898363
    Abstract: A data storage device includes a first decoder suitable for performing first ECC decoding operation; a second decoder suitable for performing second ECC decoding operation; and a control unit suitable for controlling the first decoder to perform the first ECC decoding operation to data chunks read from a memory region respectively according to read voltage sets, and performing one of prioritization, reservation and omission of the second ECC decoding operation to a current data chunk when the first ECC decoding operation to the current data chunk fails.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: February 20, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jae Bum Kim, Hyung Min Lee
  • Patent number: 9898364
    Abstract: A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: February 20, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James M. Higgins, Robert W. Ellis, Neil R. Darragh, Aaron K. Olbrich, Navneeth Kankani, Steven Sprouse
  • Patent number: 9898362
    Abstract: Systems, methods, circuits and computer-readable mediums for multi-channel RAM system with error-correcting code (ECC) protection for partial writes are provided. In one aspect, a method includes accessing a plurality of bursts of partial data units from a plurality of respective bus ports, forming a plurality of memory addresses for a plurality of memory channels by interleaving addresses from the plurality of bus ports, and performing read-modify-write (RMW) error-correcting code (ECC) processes to write partial data units from the plurality of bursts into memory portions corresponding to the formed memory addresses in the plurality of memory channels.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 20, 2018
    Assignee: Atmel Corporation
    Inventor: Franck Lunadier
  • Patent number: 9891976
    Abstract: Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: February 13, 2018
    Assignee: ARM Limited
    Inventors: Andy Wangkun Chen, Mudit Bhargava, Paul Gilbert Meyer, Vikas Chandra
  • Patent number: 9885752
    Abstract: A test apparatus for generating reference scan chain test data comprises a test pattern generator and an output data modifier. The test pattern generator modifies a scan chain test input bit sequence by replacing a predefined number of start bits of the scan chain test input bit sequence by a predefined start bit sequence. Further, the test pattern generator provides the modified scan chain test input bit sequence to a device under test. The output data modifier modifies a scan chain test output bit sequence received from the device under test and caused by the modified scan chain test input bit sequence. The scan chain test output bit sequence is modified by replacing a predefined number of end bits of the scan chain test output bit sequence by a predefined end bit sequence to obtain the reference scan chain test data.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: February 6, 2018
    Assignee: ADVANTEST CORPORATION
    Inventors: Markus Seuring, Michael Braun
  • Patent number: 9885751
    Abstract: A method for modifying the execution sequence of tests for testing an object on a test system. The tests include a group of tests that is a candidate for replacement. The method includes: while executing the tests according to the execution sequence and before executing the group of tests, modifying, in real time, the execution sequence including: executing a delay instead of the group of tests, wherein the delay is related to the group of tests.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: February 6, 2018
    Assignee: OPTIMAL PLUS LTD.
    Inventors: Eran Rousseau, Arie Peltz, Shaul Teplinsky
  • Patent number: 9882585
    Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program, and a method of improving a speed of decoding digital data. The method may include receiving a digital communication that includes digital data; specifying a partition of a plurality of elements of a Galois field into a plurality of sets; specifying an error locator polynomial function for a Reed-Solomon forward error correction module; specifying, for each set of the plurality of sets, a second function dependent upon the error locator polynomial function and one or more characteristics of the respective set; computing the second function for each of the plurality of sets to find roots of the error locator polynomial function; outputting the roots of the error locator polynomial function to a Reed-Solomon forward error correction decoder module; and decoding the digital data included in the received digital communication using the roots.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: January 30, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventor: Sarath Kumar Jha
  • Patent number: 9875803
    Abstract: According to one embodiment, a controller searches a threshold voltage distribution of first memory cells corresponding to a first processing unit that is one processing unit among a plurality of processing units, and acquires a first read voltage. The controller calculates a second read voltage that is a read voltage for second memory cells corresponding to a second processing unit based on the acquired first read voltage and a first relation. The controller reads data from third memory cells included in the second memory cells by using the calculated second read voltage.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: January 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shohei Asami, Toshikatsu Hida
  • Patent number: 9876512
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: January 23, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 9871621
    Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: January 16, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
  • Patent number: 9859022
    Abstract: A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-joong Kim, Soo-hyeong Kim, Sang-hoon Shin, Ju-yun Jung, Ho-young Song, Kyo-min Sohn, Hae-suk Lee, Bu-il Jung, Han-vit Jeong
  • Patent number: 9853661
    Abstract: A decoder includes an interface and circuitry. The interface is configured to receive a code word that was encoded using a Quasi-Cyclic Low Density Parity Check (QC-LDPC) Error Correcting Code (ECC) represented by multiple check equations that are defined over multiple variables. The circuitry is configured to decode the code word by iteratively processing multiple layers that each includes a respective subset of the variables of the code word, and producing per each layer one or more count updates, and to generate a total number of errors corrected over the entire code word by accumulating the count updates.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: December 26, 2017
    Assignee: APPLE INC.
    Inventors: Yonathan Tate, Asaf Landau, Micha Anholt
  • Patent number: 9852024
    Abstract: In a flash semiconductor memory, sense and contiguous ECC coding operations are carried out over a range of VCC values without wasted time by allocating a predetermined number of clocks to the combined operations rather than to the individual operations and operating at higher frequency for high VCC values, and lower frequency for low VCC values.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: December 26, 2017
    Assignee: Winbond Electronics Corporation
    Inventor: Koying Huang
  • Patent number: 9852022
    Abstract: According to the embodiments, a memory system includes a non-volatile memory, a control unit that reads a received word from the non-volatile memory, and a decoder that performs soft-decision decode to the received word. The decoder includes a test pattern generating unit that generates test patterns, a hard decision decoder that performs hard-decision decode by using the test pattern and the received word and outputs a decoded word, and a distance calculating unit that calculates Euclidean distance between the decoded word and the received word based on the decoded words of which the number is less than that of the test patterns of all the combinations in a case where the number of flips is of one to a predetermined value and selects a decoded word which is the decoding result from among the decoded words output from the hard decision decoder based on the Euclidean distance.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: December 26, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuma Yoshinaga, Ryo Yamaki, Daiki Watanabe
  • Patent number: 9846613
    Abstract: Methods and apparatus associated with storing data in high or low energy zones are described. Example apparatus include a data storage system (DSS) that protects a message using an erasure code (EC). A location in the DSS may have an energy efficiency rating or a latency. Example apparatus include circuits that produce EC encoded data that has a likelihood of use, that select a location to store the EC encoded data in the DSS based on the energy efficiency rating, the latency, or the likelihood of use, that store the EC encoded data in the location, and that compute an order of retrieval for EC encoded data stored in the location. The order of retrieval may be based on the energy efficiency rating or the latency. The EC encoded data may also have a priority based on the number of erasures for which the EC corrects.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: December 19, 2017
    Assignee: Quantum Corporation
    Inventors: Suayb Arslan, Turguy Goker
  • Patent number: 9846550
    Abstract: A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: December 19, 2017
    Assignees: Hewlett Packard Enterprise Development LP, University of Utah
    Inventors: Naveen Muralimanohar, Aniruddha Nagendran Udipi, Niladrish Chatterjee, Rajeev Balasubramonian, Alan Lynn Davis, Norman Paul Jouppi
  • Patent number: 9843414
    Abstract: For low complexity error correction, a decoder modifies each reliability metric of an input data stream with a random perturbation value. The reliability metric comprises a weighted sum of a channel measurement for the input data stream and parity check results for the input data stream. In addition, the decoder may generate an output data stream as a function of the reliability metrics.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: December 12, 2017
    Assignee: Utah State University
    Inventors: Chris Winstead, Gopalakrishnan Sundararajan, Emmanuel Boutillon
  • Patent number: 9836239
    Abstract: A recording device includes a plurality of storage modules and a recording controller. With respect to a writing request, the recording controller generates parity data and writes data in the respective plurality of modules by dividing the data. When an error is detected with respect to a reading request, data of the error is restored from data and the parity data read from other recording modules. With respect to an initialization request of the storage module, the storage module to be initialized is specified from the plurality of storage modules, and an address conversion table is initialized. Moreover, identification information for identifying the initialized storage module is held. With respect to a request for cancelling the table initialization request of the storage module, reading of data from the storage module corresponding to the held identification information is processed as an error.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: December 5, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideaki Yamashita, Takeshi Otsuka
  • Patent number: 9838045
    Abstract: A system and method for storing compressed data in a memory system includes identifying user data to be compressed and compressing pages of user data to form data extents that are less than or equal to the uncompressed data. A plurality of compressed pages are combined to a least fill a page of the memory. The data may be stored as sectors of a page, where each sector includes a CRC or error correcting code for the compressed data of that sector. The stored data may also include error correcting code data for the uncompressed page and error correcting code for the compressed page. When data is read in response to a user request, the sector data is validated using the CRC prior to selecting the data from the read sectors for decompression, and the error correcting code for the uncompressed page may be used to validate the decompressed data.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: December 5, 2017
    Assignee: VIOLIN SYSTEMS LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 9835682
    Abstract: A debugging system includes an embedded device and a terminal computer. The embedded device includes a memory unit, and the memory unit includes a first buffer, the embedded device is configured for executing at least one instruction to generate at least one real-time debugging information, and writing the real-time debugging information into the first buffer. The terminal computer is connected to an in-circuit emulator (ICE) via a first interface, and the ICE is connected to the embedded device via a second interface. The terminal computer uses polling to read the real-time debugging information stored in the first buffer via the ICE, and deletes the real-time debugging information stored in the first buffer afterwards.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: December 5, 2017
    Assignee: Nuvoton Technology Corporation
    Inventors: Yung-Ching Hsu, Hsin-Chou Lee