Patents Examined by Fritz Alphonse
  • Patent number: 10148388
    Abstract: With the proliferation of digital tool and content, it is becoming easier for adversaries to copy and modify digital content without detection or control by a content owner. Computing systems are provided to detects client-side data mutations. Responsive to a request to access the content data from a client device, a server compiles data that includes the content data, a mark and executable instructions for detecting data mutations, and sends this data to the client device. The client device then, based on the received instructions, stores the local environment properties relating to playing or viewing the content data, incorporates the mark with the content data, and allows the content data to be played or viewed or accessed. The client device also conducts checks in relation to the content data, the marker, and the local environment properties. If a data mutation is detected, the client device initiates an alert protocol.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 4, 2018
    Assignee: BitCine Technologies Incorporated
    Inventor: Tyson G. E. Louth
  • Patent number: 10148288
    Abstract: Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: December 4, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yaoyu Tao, Joyce Kwong
  • Patent number: 10146617
    Abstract: A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Christopher Bueb, Sean Eilert
  • Patent number: 10140241
    Abstract: A semiconductor device includes a data processing unit that processes input data and outputs processed data, a logic inversion unit that receives the processed data, inverts the processed data based on a determination result signal to be transmitted to a data bus, and an inversion determination unit that compares the input data which has not been processed by the data processing unit with the output data of the logic inversion unit corresponding to a preceding input data, and generates the determination result signal based on a comparison result.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: November 27, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroyuki Takahashi
  • Patent number: 10141072
    Abstract: Memory systems may include a memory portion, and a controller suitable for receiving information data, generating first stage data, generating a first portion parity information, generating a second portion parity information based at least in part on the first portion parity information and the first stage data, and outputting the second portion parity information.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: November 27, 2018
    Assignee: SK Hynix Inc.
    Inventors: Wei-Hao Yuan, Chung-Li Wang, Johnson Yen
  • Patent number: 10141954
    Abstract: Provided are a data error correcting method and device, and computer storage medium, the method comprising: respectively setting an index number for each data bit, and generating a first check code according to the index number; and generating a second check code according to the first check code, comparing the first check code with the second check code to determine an erroneous data bit, and correcting the erroneous data bit. The device comprises: a setting module configured to respectively set the index number for each data bit; a first check code generation module configured to generate the first check code according to the index number; a second check code generation module configured to generate the second check code according to the first check code; and a data processing module configured to compare the first check code with the second check code to determine an erroneous data bit, and correct the erroneous data bit.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: November 27, 2018
    Assignee: Sanechips Technology Co., Ltd.
    Inventor: Yiyuan Huang
  • Patent number: 10142057
    Abstract: Provided are a method for receiving data in a wireless communication system and a device using same. A device receives a code block from one cell among configured multiple cells. If a decoding error of the code block is detected, the device stores a part of or all of the code block in a receiver buffer. The number of coded bits of the code block stored in the receiver buffer is determined on the basis of the maximum modulation order supported by the cell from which the code block is received.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: November 27, 2018
    Assignee: LG Electronics Inc.
    Inventors: Joonkui Ahn, Kijun Kim, Yunjung Yi
  • Patent number: 10127184
    Abstract: An apparatus is described. The apparatus includes a point-to-point link interface circuit. The point-to-point link interface circuit is to support communication with a level of a multi-level system memory. The point-to-point link interface circuit includes a circuit to interlace payload data with cyclic redundancy check (CRC) values, where, different data segments of the payload are each appended with its own respective CRC value.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Eng Hun Ooi, Su Wei Lim
  • Patent number: 10120757
    Abstract: A method for prioritizing dispersed storage network memory (DSN) operations during a critical juncture. The method begins by a device of the DSN, during a data access request, determining when a DSN memory operation related to the data access request is at a critical juncture. A decode threshold number of encoded data slices is required to recover the data segment, a write threshold number of encoded data slices is required for a successful write operation, and the critical juncture includes the DSN memory operation being within one of a first offset of the decode threshold number and a second offset of the write threshold number. When the DSN memory operation is at the critical juncture, the method continues with detecting an outstanding action with respect to the DSN memory operation, suspending execution of non-critical DSN operations and prioritizing execution of the outstanding action.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventor: Adam M. Gray
  • Patent number: 10108494
    Abstract: A redundant array of inexpensive disks (RAID) controller of a RAID storage system that includes one or more storage devices includes an error correction code (ECC) result manager configured to manage information of ECC result indicators when a data chunk that includes one or more ECC data units having an uncorrectable ECC error is read from among a plurality of data chunks dispersively stored in the one or more storage devices, each of the plurality of data chunks including a plurality of ECC data units, the ECC result indicators respectively indicating whether the plurality of ECC data units included in the plurality of data chunks has an uncorrectable ECC error; and an uncorrectable error counter configured to calculate a number of ECC result indicators indicating an uncorrectable ECC error among ECC result indicators corresponding to ECC data units having a same order in each of the plurality of data chunks.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Geunyeong Yu, Junjin Kong, Beom Kyu Shin, Myungkyu Lee, Jiyoup Kim, Dongmin Shin
  • Patent number: 10108370
    Abstract: A method of reading a nonvolatile memory device including a plurality of pages coupled to a plurality of word lines and a plurality of bit lines, each of the plurality of pages including a data region storing a data and a flag region storing a flag, includes applying a first read voltage to a selected word line to generate first sensing data and a first sensing flag; applying a second read voltage to the selected word line to generate second sensing data and a second sensing flag, generating determination data by performing a logical operation on the first and second sensing data; determining a shift voltage based on the determination data and the read flag; and applying a third read voltage, based on the shift voltage, to the selected word line to generate a read data.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Makoto Hirano
  • Patent number: 10102066
    Abstract: A data processing device includes a first decoder suitable for performing normal or fast decoding for a plurality of data chunks, wherein the first decoder performs the normal decoding for a first data chunk among the plurality of data chunks, and performs the normal decoding or the fast decoding for a second data chunk among the plurality of data chunks, based on a result of the normal decoding for the first data chunk.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: October 16, 2018
    Assignee: SK Hynix Inc.
    Inventor: Kyoung Lae Cho
  • Patent number: 10095426
    Abstract: A method of storing data includes receiving general purpose (GP) data and special Error Tolerant or Streaming (ETS) data, storing the GP data using a data storage method, and storing the ETS data using a different data storage method which affects the access rate, resilience to errors, data integrity, storage density, or storage capacity. The storage medium, which can include a disk drive, flash memory, or holographic memory, is utilized differently depending on the required Quality of Service in aspects including block size, storage of error correction codes, utilization of error correction codes, storage area density, physical format pattern, storage verification, or reaction to failed storage verification. For disk drives these differences include spacing between tracks; overlap between tracks; spiral track formatting; concentric track formatting, and size of blocks, and for flash memories these differences include levels per cell and number of cells.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: October 9, 2018
    Inventors: Rod Brittner, Ronald G. Benson
  • Patent number: 10090863
    Abstract: A decoder for decoding a received set of blocks each including a plurality of data symbols and a plurality of parity symbols, wherein the received set of blocks is a subset of a complete set of blocks, the complete set of blocks including at least one erased block not included in the received set of blocks, the decoder including: a storage for a coding matrix which is the kronecker product of a totally non-singular matrix with an antidiagonal matrix; and a processor operable to determine data symbols of the at least one erased block using the encoding matrix.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: October 2, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Filippo Tosato, Magnus Stig Torsten Sandell
  • Patent number: 10088523
    Abstract: An integrated circuit chip comprising system circuitry and debugging circuitry. The system circuitry comprises a peripheral circuit. The debugging circuitry comprises a debug unit and a debug adapter. The debug unit is connected to the peripheral circuit. The debug adapter interfaces between the debug unit and a debug controller. The debug adapter is configured to receive a sequence of debug commands from the debug controller, each debug command instructing the debug unit to perform an action other than responding to a poll. In respect of each debug command, the debug adapter sends the debug command to the debug unit, and polls the debug unit to query whether the debug unit has performed the action instructed in that debug command.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: October 2, 2018
    Assignee: UltraSoC Technologies Limited
    Inventors: Andrew Brian Thomas Hopkins, Andrew James Bower, Michael Jonathan Thyer
  • Patent number: 10078561
    Abstract: A method for execution by a dispersed storage and task (DST) execution unit identifying a failing memory device based on memory device diagnostic data. A cloning task is executed by designating memory of a replacement memory device to store encoded slices stored in the failing memory device, where the cloning task is executed over a cloning duration time period. A write request is received via a network at a receiving time during the cloning duration time period that includes a new encoded slice, and the new encoded slice is assigned to a temporary memory device for storage based on an identifier of the new encoded. The new encoded slice is transferred from the temporary memory device to the replacement memory device in response to an elapsing of the cloning duration time period corresponding to completion of the execution of the cloning task.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: September 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ilir Iljazi, Jason K. Resch
  • Patent number: 10078468
    Abstract: A method for use in a dispersed storage network includes receiving location data corresponding to a location of a client computing device; determining, based on the location data, that the client computing device is at a location outside a home area of the client computing device; and transferring pre-fetch slices associated with the client computing device from a first plurality of dispersed storage units associated with the home area of the client computing device for storage in a second plurality of dispersed storage units associated with the location of the client computing device.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brian F. Ober, Jason K. Resch
  • Patent number: 10069833
    Abstract: A computer security method including detecting access, by a computer in a first computer network, to a computer-readable document, determining whether the computer-readable document was retrieved from a second computer network, identifying a reference, associated with the computer-readable document, to a resource at a location within the first computer network, and preventing access by the computer to the resource at the location within the first computer network responsive to determining that the computer-readable document was retrieved from the second computer network.
    Type: Grant
    Filed: November 29, 2015
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shmuel Regev, Amit Klein
  • Patent number: 10067826
    Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: September 4, 2018
    Assignee: Infineon Technologies AG
    Inventors: Thomas Rabenalt, Ulrich Backhausen, Thomas Kern, Michael Goessel
  • Patent number: 10062446
    Abstract: A circuit architecture for operating error-correction code (ECC) in a memory apparatus includes a control circuit and an ECC circuit. The ECC circuit is coupled with the control circuit. The control circuit receives a first data of a set of bits to invert the first data as an inverted data. The ECC circuit receives the inverted data for encryption or decryption and outputs an ECC-processed data. The control circuit inverts the ECC-processed data as a second data.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 28, 2018
    Assignee: eMemory Technology Inc.
    Inventor: Po-Hao Huang