Patents Examined by Fritz Alphonse
  • Patent number: 9991008
    Abstract: Systems and methods for analyzing and reducing the failure rates due to soft errors in a design are provided. One such method involves analyzing the design by reading the design from a register-transfer-level language description or a netlist, manufacturing process soft error information, library information and timing constraints for the design to generate the failure in time (FIT) rate for the modules in the design.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: June 5, 2018
    Assignee: Austemper Design Systems Inc.
    Inventor: Sanjay Pillay
  • Patent number: 9990252
    Abstract: In part, the disclosure relates to a computer-implemented system for managing a data storage system comprising a plurality of data storage nodes. The system includes at least one processor and an operatively associated storage device. The at least one processor is programmed to: monitor utilization of at least one data object stored at the data storage system as a coded data object comprising a first total number of data blocks, wherein each of the first number of data blocks is stored at a separate data storage node, and wherein an original data object is re-creatable from a first base number of data blocks selected from the first total number of data blocks; determine that the utilization of the at least one data object has changed; and modify a number of the plurality of data storage nodes that store data blocks of the coded data object.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: June 5, 2018
    Inventors: Alexey Morlang, Alexey Andreev, Andrey Neporada, Serguei Beloussov
  • Patent number: 9990160
    Abstract: One embodiment relates to a memory structure that includes a bank group and a port emulation circuit module. The bank group includes a plurality of memory banks, each memory bank having one read port and one write port. The port emulation circuit module provides a group read/write port and a group read port for the bank group. Another embodiment relates to a port emulation circuit module. The port emulation circuit module includes a port emulation control circuit that receives control signals including a first address for a group read/write port and a second address for a group read port, a first data path circuit for the group read/write port, and a second data path circuit for the group read port, wherein the second data path circuit outputs a second read data. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: June 5, 2018
    Assignee: Altera Corporation
    Inventor: Chee Hak Teh
  • Patent number: 9985653
    Abstract: At least one example embodiment discloses a method of soft-decision Wu decoding a code. The code is one of a generalized Reed-Solomon type and an alternant type. The method includes obtaining a module of the code. The module is a sub-module of at least a first extension module and a second extension module. The first extension module is defined by a set of first type constraints and the second extension module is defined by a set of second type constraints. The first type constraints are applicable to a first interpolation algorithm and a second interpolation algorithm and the second type constraints are applicable to the first interpolation algorithm. The method further includes determining a basis for the first extension module and converting the basis for the first extension module to a basis for the module.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: May 29, 2018
    Inventors: Yaron Shany, Jun Jin Kong
  • Patent number: 9984601
    Abstract: Embodiments of the present disclosure provide a repairing system and a repairing method for a CABC module. The system comprising: a CABC module that includes a first register and a second register; an initial value register configured to input a check value or an initial value to the first register; a first logic circuit, a second logic circuit, a third logic circuit and a fourth logic circuit.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: May 29, 2018
    Inventors: Zhijia Cui, Shuai Xu
  • Patent number: 9985652
    Abstract: In some embodiments of the present invention, a data storage device includes a controller and a memory. The data storage device further includes an LDPC encoder and decoder, with the decoder implementing a dynamic precision-rescaling technique for improving performance. In one embodiment, the technique works by rescaling the binary representations of the input log-likelihood ratios (LLRs) and messages upon activation of decoder-state-based triggers. Various triggering functions are introduced, e.g., checking if the number of output LLRs smaller than a certain limit crosses a threshold, checking if the weight of a syndrome crosses a threshold, etc. This technique offers an improvement in the performance of the decoder.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: May 29, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kent D. Anderson, Anantha Raman Krishnan
  • Patent number: 9973300
    Abstract: Systems, methods, and apparatuses are disclosed for choosing the modulation mode using packets transmitted by a sender to a receiver, wherein the packets contain data patterns unknown to the receiver. In some embodiments, the sender sends of a data packet in the most robust mode available, such that the packet can be correctly received by the receiver under even the noisiest conditions. The data contained in the packet is demodulated and decoded. A cyclic redundancy check is performed to ensure that the resultant data is error-free. Once the transmitted payload data is known, the original error coding can be re-applied to the payload data to produce the transmitted bit stream. Comparison of the demodulated bit stream to the regenerated transmitted bit stream yields the pattern of errors. The pattern of errors is analyzed and a higher throughput decoding scheme is chosen based on the results of the analysis.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: May 15, 2018
    Assignee: Echelon Corporation
    Inventors: Walter Downey, Leonid Ovanesyan
  • Patent number: 9967058
    Abstract: A method for reconciling bit strings over a communications network. A first subscriber ascertains error correction information for each one of a plurality of different blocks, which each include a predetermined number of bits from a first bit string, and transmits the same over the communications network. Each of the blocks having at least one bit in common with at least one other one of the blocks.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: May 8, 2018
    Inventors: Paulius Duplys, Christopher Huth
  • Patent number: 9966975
    Abstract: Systems and methods are disclosed for optically communicating data by, at a transmitter side, encoding a block of input bits by one or more outer encoders, and after interleaving the encoded bits, permuting the encoded bits according to a predetermined sequence or order, and further encoding the encoded bits by an inner encoder, and at a receiver side, decoding received bits with an inner decoder, and after the encoded bits are permuted, subsequently decoding by and outer decoder, and returning information bits at an outer decoder as an output. The soft-decision and hard-decision outputs from the outer BCH code help the inner LDPC decoder to have better estimation of the received bits and gain performance. The performance in higher-order modulation formats could be as large as 0.5 dB in one embodiment.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 8, 2018
    Assignee: NEC Corporation
    Inventors: Shaoliang Zhang, Fatih Yaman, Wei Zhou
  • Patent number: 9959168
    Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The controller includes a stripe generator and a stripe decoder. The stripe generator is configured, in response to the number of undecodable codewords exceeding an erasure correction capacity of a stripe correction scheme, to generate trial data for a stripe of the data structure, the trial data including at least one element that corresponds to erased data and at least another element that is associated with an undecodable codeword and that corresponds to valid data of the stripe. The stripe decoder is configured to initiate a stripe decode operation of the trial data.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: May 1, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Stella Achtenberg, Eran Sharon, Idan Alrod
  • Patent number: 9960984
    Abstract: A computing device performance monitor may be configured to collect performance metric information regarding one or more monitored computing devices, and may assign condition point values to each metric. The performance monitor may generate a total of the condition point values, and use the total to determine an appropriate response.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: May 1, 2018
    Assignee: Comcast Cable Communications, LLC
    Inventors: David Leach, James Russell, Timothy Parol, David Eng, Mark Anderson, Dante Burks
  • Patent number: 9959166
    Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: May 1, 2018
    Inventors: Robert Mateescu, Zvonimir Z. Bandic, Yongjune Kim, Seung-Hwan Song
  • Patent number: 9947399
    Abstract: Data is initially programmed in a portion of ReRAM in parallel. Subsequently, one or more ReRAM cells in the portion are determined to contain first data that is to be modified while remaining ReRAM cells in the portion contain second data that is not to be modified. First conditions are applied to the one or more ReRAM cells thereby modifying the first data, while second conditions are applied to the remaining ReRAM cells, the second conditions maintaining the second data in the remaining ReRAM cells without significant change.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: April 17, 2018
    Inventors: Ariel Navon, Idan Alrod, Eran Sharon, Idan Goldenberg, Didi Gur
  • Patent number: 9948324
    Abstract: Information reduction in data processing environments includes at least one of: one or more Error Correcting Codes that decode n-vectors into k-vectors and utilize said decoding to information-reduce data from a higher dimensional space into a lower dimensional space. The information reduction further provides for a hierarchy of information reduction allowing a variety of information reductions. Transformations are provided to utilize available data space, and data may be transformed using several techniques including windowing functions, filters in the time and frequency domains, or any numeric processing on the data.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: April 17, 2018
    Assignee: Open Invention Network, LLC
    Inventor: Allan Havemose
  • Patent number: 9946599
    Abstract: Systems and methods described herein provide a method for enhanced data access to a hard disk drive with caching. The method includes obtaining data for storage from a data source. The method further includes applying at least one of a track error-correcting code scheme, a redundant array of independent disks (RAID) encoder, streaming inter-track interference cancellation and a lower power read-data channel to the obtained data. The method further includes configuring a caching system to store a frequently accessed portion of the encoded data, and receiving, from a host computer, a data access request. The method further includes retrieving a data file from the caching system to the host computer in response to the data access request.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: April 17, 2018
    Assignee: Marvell International Ltd.
    Inventor: Gregory Burd
  • Patent number: 9948427
    Abstract: System and method of comparing-selecting state metric values for high speed Viterbi decoding. In an Add-Compare-Select (ACS) unit, a select control signal is produced by Boolean operations on comparator decision signals and used to control a multiplexer structure. The comparator decision signals can be generated in parallel by an array of comparators comparing all possible pairs of a set of state metrics values. The Boolean operations are predefined through Boolean algebra that uses the decision signals as variables and complies with restriction imposed by the selection criteria, e.g., to select an minimum or maximum value of the set of state metrics values. The Boolean operations are performed by a logic module implemented using basic logic gates, such as AND, OR and NOT. As a result, the multiplexer structure that receives the set of input values can output the optimum value responsive to the select control signal.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: April 17, 2018
    Assignee: MACOM Connectivity Solutions, LLC
    Inventors: Yehuda Azenkot, Bart Zeydel
  • Patent number: 9946596
    Abstract: In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 17, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Daisuke Hashimoto, Hironori Uchikawa
  • Patent number: 9934086
    Abstract: Apparatuses and methods are described for selective determination of data error repair. An example apparatus includes a memory array and a controller coupled to the memory array. The controller is configured to direct performance, responsive to a request, of a read operation at an address in the memory array, direct detection of an error in data corresponding to the read operation address, and direct storage of the read operation address in an address error register. The controller is further configured to direct a response be sent to the enable selective determination of data error repair, where the response does not include the read operation address.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: April 3, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Ryan S. Laity, Christopher S. Johnson
  • Patent number: 9935654
    Abstract: In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: April 3, 2018
    Assignee: Alcatel-Lucent USA Inc.
    Inventors: Behnam Sedighi, Nagaraj Prasanth Anthapadmanabhan, Dusan Suvakovic
  • Patent number: 9927990
    Abstract: According to an embodiment, a memory system includes: a non-volatile memory; an encoding unit that generates a code word in which zero and one occur at different occurrence rates by encoding data; and a control unit that writes k third data items and fourth data items into the non-volatile memory. The k is an integer larger than or equal to zero and smaller than or equal to n. The n is an integer larger than or equal to two. The k third data items are obtained by encoding k second data items with the encoding unit among first data items including n second data items and having a first data length. The fourth data items are obtained by removing data corresponding to the k third data items from the first data items. The third data items are generated by encoding the second data items with encoders, respectively.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: March 27, 2018
    Inventors: Osamu Torii, Tokumasa Hara, Hironori Uchikawa