Patents Examined by G. Lawrence Opie
  • Patent number: 7140026
    Abstract: The present invention relates to a method and device for communicating with remote units over at least one data network and with at least one dedicated CPU. The message processing device according to the present invention includes a first execution unit for receiving a message to be processed and determining the kind of treatment to be performed with the received message, a second execution unit for performing the determined treatment, and a third execution unit for presenting the result of the message processing to be forwarded to a destination unit.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventor: Dieter E. Staiger
  • Patent number: 7013468
    Abstract: A method and apparatus relating to a CAD system that enables communication between a first CAD application and a second CAD application in a manner providing associative interoperability is provided. In one illustrative example, a method is provided in at least one electronic device of communicating between a first CAD application and a second CAD application. The method begins by storing native data and a sub-set of native data. A plug-in is provided having an application program interface API and being accessible by the second CAD application. The plug-in conveys the sub-set of native data to the second CAD application. The system for carrying out the method includes a first CAD application and a second CAD application. Native data and a sub-set of native data relating to an object modeled on the first CAD application are stored in a first memory store.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: March 14, 2006
    Assignee: Parametric Technology Corporation
    Inventors: Phil J. Abercrombie, Blake Z. Courter
  • Patent number: 7010793
    Abstract: Described herein is a mechanism that follows, at least in part, an object oriented design pattern. In particular, a class is used to model a shared resource as a shared resource object. The class creates one instance of the shared resource object in response to multiple attempts to create a shared resource object from the class. The class defines various methods used to interact with the object. The object receives requests to perform operations from the clients. The clients may register another object to receive from the shared resource object notifications regarding events about the operations requested by the clients.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: March 7, 2006
    Assignee: Oracle International Corporation
    Inventors: Surojit Chatterjee, Jonathan Creighton, Alok Srivastava
  • Patent number: 6842853
    Abstract: In processor architectures that support allocation of register windows to called procedures, functions or methods, register windowing mechanisms can be used to facilitate suspension of a mutator thread (or mutator threads) while imposing negligible overhead on the mutator computation during periods when thread suspension is not requested. Reduced Instruction Set Computer-(RISC)-oriented processor architectures often employ register windows (typically partially-overlapped register windows) and can therefore benefit from the technique. Variations can be employed even in processors (RISC or otherwise) that do not employ register windowing as long as the processor (by itself or in cooperation with software) provides facilities for allocating and reclaiming resources in correspondence with calls to, and returns from, procedures, functions or methods.
    Type: Grant
    Filed: January 13, 1999
    Date of Patent: January 11, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: William Bush, Mario Wolczko
  • Patent number: 6736325
    Abstract: A system and method for efficiently storing programming instructions in a microprocessor based system where codelets which include program instructions written in a non-native programming language (such as MEL or C) are stored in a read only portion of memory. The location of the codelets are stored in an address table which is accessed by an operating system when an application calls the codelet during execution. At that time, the microprocessor accesses the codelet instructions until the codelet function is complete. By storing codelets in read only memory which is cheaper and takes up much less physical space than alterable memory (such as EEPROM), more programming instructions can be stored in the same amount of physical space. Additionally, since codelets are written in non-native programming languages, they become platform independent since they can be compiled by different compilers to run on any platform.
    Type: Grant
    Filed: January 13, 1999
    Date of Patent: May 18, 2004
    Assignee: Mondex International Limited
    Inventor: Anthony David Peacham
  • Patent number: 6675190
    Abstract: Instead of a conventional task scheduler in which tasks having a high priority are preferentially scheduled, so that the execution of tasks with very low priorities is blocked, a “fair scheduler” is proposed in which each task (TA to TE) is assigned a counter (CNT) and a threshold value (THD), with the threshold value specifying a maximum number of execute cycles within which the task need not be executed immediately, and the counter counting those execute cycles within which the task is not executed. At the beginning of each execute cycle, a test is made to determine whether one of the counters exceeds the associated threshold value. If that is the case, one (TD) of the corresponding tasks (TC, TD) is selected by a selection criterion and executed, and its counter is reset. The counters assigned to the remaining tasks are incremented by one, and the execute cycle is repeated if it is found that at least one more of the tasks (TC) is waiting to be processed.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: January 6, 2004
    Assignee: Alcatel
    Inventors: Jörg Schabernack, Reimund Klamt, Hartmut Dr. Kocher
  • Patent number: 6446259
    Abstract: A language translator is provided which determines memory structure at compile time for a plurality of object classes including at least one virtual base class and at least one class derived therefrom. At compile time, space for pointers (b-pointers) is set aside in each class object that will have a base table (b-table) associated therewith. The b-pointers point, at run time, to an associated b-table containing memory offsets between the base classes of the derived class. At run time, constructors construct the class objects, starting from the most derived class object and proceeding through to the base class object. However, instead of generating the virtual tables and associated pointers, as well as the adjusting functions, at compile time, the language translator generates the code for these operation to be executed at run time. Then at run time, a virtual function table is generated for the base class.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: September 3, 2002
    Assignee: Compaq Computer Corporation
    Inventor: Bevin R. Brett
  • Patent number: 6421737
    Abstract: Selected resources of a computing system are monitored. A user interacting with a resource management client discovers the resources currently available to be monitored and then selects which resources of the computing system are to be monitored. Also, the user selects monitor parameters for each resource. Then, for each resource selected, the resource management client forwards to a resource monitoring manager a monitor request to monitor the resource. The resource monitoring manager reformats the monitor request to form a reformatted monitor request. The resource monitoring manager forwards the reformatted monitoring request to one of a plurality of resource monitor modules. The resource monitor module which receives the reformatted monitoring request monitors the resource.
    Type: Grant
    Filed: May 2, 1997
    Date of Patent: July 16, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Bradley A. Stone, Thomas A. Murray, Bruce N. Campbell
  • Patent number: 6411982
    Abstract: A scheduling governor that regulates the number of scheduled tasks that are executed concurrently over a network computer system is presented. All task requests that are scheduled to be executed within a pre-specified interval of time, are serviced according to their priority. During heavy load times, the scheduling governor prevents overloads of the processing resources of the host computer by limiting the number of concurrently executing scheduled tasks to a pre-specified capacity dimension. Task requests that are unable to be run due to the governed cap on the number of allowed concurrently executing processes are given a priority to be executed once one of the fixed number of execution slots becomes available. Accordingly, the scheduling governor allows each scheduled task to be executed as close to its scheduled time as possible yet prevents system resource overload to improve efficiency and performance.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: June 25, 2002
    Assignee: Hewlett-Packard Company
    Inventor: Roy H. Williams