Abstract: A method for creating a layout of at least a portion of a microelectromechanical system is disclosed. In one embodiment, a plurality of die are formed on a wafer. Each die includes a plurality of rows of a plurality of mirror assemblies, a plurality of off-chip electrical contacts, and an electrical trace bus that is disposed between adjacent pairs of rows. This electrical trace bus is electrically interconnected with mirror assemblies in at least one of the rows. A plurality of these die are formed on a wafer. A chip is separated from the wafer such that a chip width is an integer multiple of the die width and such that a chip height is an integer number of the rows of mirror assemblies without requiring the chip height to be an integer multiple of the die height.

Abstract: A method for controlling etch bias of carbon doped oxide films comprising performing the etch in a cyclic two step process i.e., a carbon doped oxide (CDO) removal process, said CDO removal process comprises a first gas to etch a trench in the CDO layer. The CDO removal process is followed by a polymer deposition process. The polymer deposition process comprises introducing a second gas in the reactor to deposit a polymer in the trench of the CDO layer. The first gas comprises a first molecule having a first ratio of carbon atoms to fluorine atoms, and the second gas comprises a second molecule having a second ratio of carbon atoms to fluorine atoms, such that the second ratio of carbon atoms to fluorine atoms is greater than the first ratio of carbon atoms to fluorine atoms. The above process may be repeated to etch the final structure.

Abstract: A plug is formed of polysilicon, or other oxidizable conductor. Chemical-mechanical polishing is performed, with a polish stop layer defining the top of the dielectric layer. The upper portion of the polysilicon is oxidized to a controlled depth, then the oxidized portion is removed by an etch, followed by removal of the polish stop layer. The plug thus formed protrudes a controllable distance above the surrounding dielectric, providing good contact to subsequent conductive layers.

Abstract: A trench isolation structure characterized by a dielectric stud filling and spanning a trench in a semiconductor substrate is suggested for isolating the integrated circuits fabricated in the semiconductor substrate. The dielectric stud is formed by depositing isolating material in a space defined by the trench and a dielectric layer overlying the semiconductor substrate and being partially removed over an area which spans the trench and extends over the lengthwise edges of the trench.

Abstract: A semiconductor integrated circuit device comprises a multiple-stage amplifier including a plurality of transistors. The multiple-stage amplifier has a first stage comprising a plurality of bipolar transistors each having a single emitter structure. The bipolar transistors are connected parallel to each other. The semiconductor integrated circuit device can easily be designed, is of a self-aligned structure, and has a single transistor size. The semiconductor integrated circuit device may be used as a low-noise, high-power-gain high-frequency amplifier.

Abstract: The specification describes thin film transistor CMOS integrated circuits wherein the semiconductor is an ambipolar organic material. The preferred material is tetracene or pentacene. In these CMOS devices, a single homogeneous layer of tetracene or pentacene can be used in both n-type (inversion) and p-type (accumulation) devices.

Abstract: Array of electrically programmable non-volatile memory cells, each cell comprising a stacked-gate MOS transistor having a lower gate electrode, an upper gate electrode coupled to a row of the array, a first electrode associated with a column of the array and a second electrode separated from the first electrode by a channel region underlying said lower gate electrode, the first electrode, the second electrode and the channel region being formed in a layer of semiconductor material of a first conductivity type and having a second conductivity type, comprising at least one ROM memory cell which identically to the electrically programmable non-volatile memory cells comprises a stacked-gate MOS transistor and is associated with a respective row and a respective column of the array, the ROM cell including means for allowing or not allowing the electrical separation between said respective column and the second electrode of the ROM cell, if the ROM cell must store a first logic state or, respectively, a second logi

Abstract: A gate electrode 5 is provided on a surface of a semiconductor substrate 1, an insulation film 6 being formed over the gate electrode 5 and the side wall of the gate electrode 5 being covered by an insulation film 8, and, on a diffusion region 7 that is formed on the surface of the semiconductor substrate 1 at both sides of the above-noted gate electrode 5 and in a region that is sandwiched between the above-noted side walls 8, 8, a silicon single crystal is anisotropically grown in a direction that is perpendicular with respect to the semiconductor substrate 1, so as to form a pad 9, and the anisotropic growth of the silicon single crystal is only within a part 8a of the region sandwiched between parts of the side wall 8 that are perpendicular to the substrate surface.

Abstract: A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.

Abstract: The solid-state image sensor comprises a semiconductor substrate, a plurality of photoelectric conversion sections formed within respective isolated active regions on the semiconductor substrate, an image area wherein unit cells comprising the plurality of photoelectric conversion sections and a signal scanning circuit are arranged in a two-dimensional array form, and signal lines for reading signals from the respective unit cells within the image pick-up area, wherein the respective photoelectric conversion sections being formed by at least twice ion implantation.

Abstract: An electrode for a Group III nitride compound semiconductor having p-type conduction that has a double layer structure. The first metal electrode layer comprising, for example, nickel (Ni) and the second metal electrode layer comprising, for example, gold (Au). The Ni layer is formed on the Group III nitride compound semiconductor having p-type conduction, and the Au layer is formed on the Ni layer. Heat treatment changes or reverses the distribution of the elements Ni and Au. Namely, Au is distributed deeper into the Group III nitride compound semiconductor than is Ni. As a result, the resistivity of the electrode is lowered and its ohmic characteristics are improved as well as its adhesive strength.