Abstract: An analog/digital converter circuit including a capacitor having a first end, to which an analog voltage is applied, and a second end, an input buffer circuit having an input terminal, connected to the second end of said capacitor, and an output terminal, a reference voltage generating circuit for generating a plurality of reference voltages having different voltage levels, a voltage comparator circuit having a plurality of voltage comparators for comparing the output voltage of the input buffer circuit with each of the reference voltages generated by the reference voltage generating circuit, and generating a digital signal corresponding to the comparison results, a decoder circuit for decoding the output of the voltage comparator circuit, and D.C. bias voltage selection/supply circuit for selecting one of the reference voltages of the reference voltage generating circuit and supplying the selected reference voltage as a D.C. bias voltage to the input terminal of the input buffer circuit.

Abstract: An adjustable current source comprising a bipolar transistor (BT), the base of which receives a signal adapted to approximately set the current which flows therethrough, and a MOS transistor (MT), in series with the bipolar transistor, the gate (G) of which receives an adjustment signal stored by a capacitor (C) connected between its gate and its drain. This current source can be used for forming the upper stages of an auto-calibration digital converter.

Abstract: A method and system for encoding a series of input digital signals in a higher order digital format, such as 16 bit, to a series of lower order digital signals such as 8 bit, and then recovering the original input signals with a greater accuracy than previously attainable is described. A distinct reduction in quantization noise is produced, making the system compatible with very high resolution audio equipment such as compact disks. For each input signal, a particular pair of complementary encoding and decoding transformations are selected from a set of numerous possible transformations. The transformations are nonlinear, with high resolutions near the origin and much lower resolutions further away. The high resolution range increases from table to table, while the absolute resolution within said ranges decreases. The value of each input signal is predicted from previous signals, and a differential quantity representing the prediction error is used in selecting the table for each signal.

Abstract: An improved Manchester code receiver is disclosed which samples the received signal and subtracts from that sample a previous sample of the received signal delayed by a half-bit time interval. A timing extractor selects sample timing from the central zero crossing of the received signal. The sample time is selected to be a quarter-bit time after the zero crossing time of the received signal.

Abstract: A single chip monolithic integrated successive approximation analog-to-digital converter includes a test mode terminal for receiving shift register test mode control signals and successive approximation mode control signals. Digital test data signals are applied to a test data terminal. A trimmable digital-to-analog converter (DAC) is connected to receive digital signals and converts these signals to analog signals of corresponding values. A successive approximation and shift register is coupled to the test mode terminal and the test data terminal. During post-fabrication processing, the successive approximation and shift register operates in a shift register test mode in response to the test mode control signals. Test signals of a known value are serially received and applied in parallel to the DAC. The DAC can then be trimmed to required specifications. The successive approximation and shift register operates in a successive approximation mode in response to successive approximation mode control signals.

Abstract: An oversampled A/D converter which utilizes digital error correction is provided. In one form, the present invention is used with a sigma delta modulator having a plurality of rank ordered quantization loops, Each quantization loop contains an analog integrator circuit of predetermined gain which is subject to variation, thereby introducing errors. When the product of a reciprocal of the analog integrator gain and the gain of a digital gain stage of a subsequent quantization loop equals one, minimum noise exists in the data conversion. A digital gain control circuit is coupled to the digital gain stage for adjusting the gain of the digital gain stage during a calibration mode to provide minimum noise in the converter, thereby compensating for errors attributable to the analog integrator circuit.

Abstract: A bit pattern conversion system for converting a sequence of a bit pattern between a central processing unit and a peripheral circuit, including a data bus line connected between the central processing unit and the peripheral circuit, and a conversion circuit provided in the peripheral circuit for converting the sequence of the bit pattern from a most significant bit to a least significant bit, and vice versa, in accordance with a conversion signal.