Abstract: A 6T SRAM cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second inverter cross-coupled with the first inverter having a second pull-up transistor and a second pull-down transistor serially coupled between the supply source and the complementary supply source. The cell further includes a first pass-gate and second pass-gate transistors coupled to the first and second inverters, respectively. The first pass-gate transistor and the first pull-up transistor are respectively constructed on a first P-type well and a first N-type well adjacent to one another, which are overlaid by a first doped region and a second doped region of substantially the same width in alignment with one another, respectively.

Abstract: A nonvolatile ferroelectric memory device includes a first cell array block and a second cell array block, each divided into an upper part and a lower part; sensing amplifiers arranged one by one on multiple bit lines at a middle portion between the first cell array block and the second cell array block; a data I/O encoder connected to end portions of the multiple bit lines for outputting multi-bit signals by encoding outputs of the sensing amplifiers; and a first reference cell array block and a second reference cell array block arranged between the first cell array block and the data I/O encoder and between the second cell array block and the data I/O encoder.