Patents Examined by Gabriel Chu
  • Patent number: 11940886
    Abstract: Methods, apparatus, and processor-readable storage media for automatically predicting fail-over of message-oriented middleware systems are provided herein. An example computer-implemented method includes obtaining one or more message-oriented middleware parameter values for at least a portion of multiple message-oriented middleware systems; detecting one or more fail-over-related anomalies associated with at least one of the multiple message-oriented middleware systems by processing at least a portion of the one or more message-oriented middleware parameter values using one or more machine learning techniques; and automatically migrating, based at least in part on the one or more detected fail-over-related anomalies, at least a portion of data associated with the at least one message-oriented middleware system associated with the one or more detected fail-over-related anomalies to at least one of the other of the multiple message-oriented middleware systems.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: March 26, 2024
    Assignee: Dell Products L.P.
    Inventors: Madhanamohana Reddy Gandluri, Sheik Saleem, Bijan Kumar Mohanty, Hung T. Dinh
  • Patent number: 11914499
    Abstract: A trace-data preparation circuit including a filtering circuit to receive traced memory-write data and a First In First Out buffer coupled with the filtering circuit to receive selected memory-write data filtered by the filtering circuit. The trace-data preparation circuit further including a data compression circuit to provide packaging data to a packaging circuit that groups the selected memory-write data.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 27, 2024
    Assignees: STMicroelectronics Application GMBH, STMicroelectronics S.r.l., STMicroelectronics International N.V.
    Inventors: Avneep Kumar Goyal, Thomas Szurmant, Misaele Marletti, Alessandro Daolio
  • Patent number: 11907085
    Abstract: Various methods, apparatuses/systems, and media for implementing a smart failover module is disclosed. A processor detects an application specific system fault or degradation event in a first availability zone (AZ) on which an application is running during normal runtime of the application; determines, in response to detecting the application specific system fault or degradation event, whether the application includes an active-passive application infrastructure in which the first AZ is paired with a passive AZ; enables traffic, in connection with running or deployment of the application, on the passive availability zone in response to determining that the application includes an active-passive application infrastructure; and disables traffic from the first AZ on which the application specific system fault or degradation has been detected in response to determining that the application does not include an active-passive application infrastructure and/or in response to enabling traffic on the passive AZ.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: February 20, 2024
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Matthew J Porter, Kumar Rao Krishnagi, Vijay Kumar Perla, Nalini S Boda, Laxman Dongisharapu, Mark Alan Wells
  • Patent number: 11847016
    Abstract: A system to facilitate application logging is described. The system includes a processor and a machine readable medium storing instructions that, when executed, cause the processor to record a system state, perform application logging at a first logging rate, record an occurrence of task failures during the logging, determine a predicted queue size threshold value based on the recorded occurrence of task failures, determine whether that the predicted queue size threshold value is less than an actual queue size and perform the application logging at a second logging rate upon a determination that the predicted queue size threshold value is less than an actual queue size, wherein the second logging rate is greater than the first logging rate.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: December 19, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Aravind Badiger, Abhilash Kulkarni, Ravindhar Uppada
  • Patent number: 11815987
    Abstract: The disclosed embodiments provide for identification of a remedial action based on analysis of a system log file. In some example embodiments, messages from the system log file are used as input to generate vectors within a vector space. Portions of the log messages may generate vectors that cluster into a region in the vector space. The region of vector space is associated with one or more remedial actions. The disclosed embodiments are configured, in some example embodiments, to perform the one or more remedial actions when activity in the log file maps to the region of vector space associated with the one or more remedial actions. In some example embodiments, a remedial action can include submitting a problem report to a problem tracking database.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: November 14, 2023
    Assignee: Juniper Networks, Inc.
    Inventors: Jisheng Wang, Gaurav Sunil Nandode, Winson Benedict Fernandes
  • Patent number: 11809290
    Abstract: A storage system includes a host including a host queue storing a plurality of commands and a storage device including a storage queue exchanging commands with the host through a first port or a second port, and storing the exchanged commands, wherein the storage device is configured to, when a communication error has occurred through the first port, transfer information about a command stored in the storage queue before the error occurrence to the host through the second port.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: November 7, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongwon Lee, Jangwook Park, Kwanhu Bang, Joonwhan Bae, Brian Myungjune Jung
  • Patent number: 11803773
    Abstract: Methods, apparatus, and processor-readable storage media for machine learning-based anomaly detection using time series decomposition are provided herein. An example computer-implemented method includes processing, via machine learning techniques pertaining to time series decomposition functions, a first set of historical time series data derived from multiple systems within an enterprise; generating, based on the processed data, one or more pairs of upper bounds and lower bounds directed to system metrics; identifying system anomalies attributed to one or more of the multiple systems within the enterprise by comparing a second set of historical time series data derived from the one or more systems against the one or more pairs of upper bounds and lower bounds; prioritizing, via machine learning techniques pertaining to weighting functions, the system anomalies; and outputting, in accordance with the prioritization, the system anomalies to a user within the enterprise.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: October 31, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Zachary W. Arnold, Bina K. Thakkar, Peter Beale
  • Patent number: 11797369
    Abstract: A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: October 24, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James R. Magro, Kedarnath Balakrishnan, Vilas Sridharan
  • Patent number: 11768727
    Abstract: Described are techniques including a computer-implemented method of determining, by a service processor, that a first set of callouts of a first error log matches a previous set of callouts of a previous error log. The method further comprises combining the first error log with the previous error log in a first group in a service processor log of the service processor. The method further comprises transmitting information related to the first group to a management console communicatively coupled to the service processor.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: September 26, 2023
    Assignee: International Business Machines Corporation
    Inventors: Sampa Misra, Deepak Kodihalli, Giridhari Krishnan
  • Patent number: 11768746
    Abstract: The embodiments described herein describe technologies to maintaining a secure session state with failover during endpoint provisioning. A cluster of hardware devices can be used for provisioning endpoint devices with secrecy, integrity, access controller, high availability, minimal transaction time, and interactive transactions with multiple requests and response within a session. The embodiments are directed to a first computing device being elected as a leader and sharing context information of a session with other computing devices as followers in the cluster such that a follower can resume the session if the leader fails.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: September 26, 2023
    Assignee: Cryptography Research, Inc.
    Inventor: Denis Alexandrovich Pochuev
  • Patent number: 11675670
    Abstract: Methods and systems for recovering a host image of a client machine to a recovery machine comprise comparing a profile of a client machine of a first type to be recovered to a profile of a recovery machine of a second type different from the first type, to which the client machine is to be recovered, by a first processing device. The first and second profiles each comprise at least one property of the first type of client machine and the second type of recovery machine, respectively. At least one property of a host image of the client machine is conformed to at least one corresponding property of the recovery machine. The conformed host image is provided to the recovery machine, via a network. The recovery machine is configured with at least one conformed property of the host image by a second processing device of the recovery machine.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: June 13, 2023
    Assignee: FALCONSTOR, INC.
    Inventors: Po-Hsin Wei, Andrew Spyros Malitzis, Andrew Lee Modansky, Sheng-Chang Chang
  • Patent number: 11663064
    Abstract: Disclosed herein are systems and method for generating a guest Operating System (OS) crash dump. In one aspect, an exemplary method comprises, obtaining information about a guest physical memory and a state of a guest CPU, determining guest page tables including a data structure for mapping between the guest physical memory and guest virtual pages using registers of the guest CPU, identifying an interrupt handler and determining an address of the interrupt handler using the guest page tables and the registers of guest CPU, finding a location of a kernel image in memory by scanning virtual addresses backward starting from the interrupt handler until a beginning of an executable kernel module is found, identifying and fetching debug symbols, determining system task descriptors using the debug symbols, determining debugger relevant data using the debug symbols, and generating the crash dump header using the system task descriptors and the debugger relevant data.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: May 30, 2023
    Assignee: Virtuozzo International GmbH
    Inventors: Roman Kagan, Denis Lunev, Alexey Kobets, Victor Prutyanov
  • Patent number: 11656945
    Abstract: Methods and processing devices are provided for error protection to support instruction replay for executing idempotent instructions at a processing in memory PIM device. The processing apparatus includes a PIM device configured to execute an idempotent instruction. The processing apparatus also includes a processor, in communication with the PIM device, configured to issue the idempotent instruction to the PIM device for execution at the PIM device and reissue the idempotent instruction to the PIM device when one of execution of the idempotent instruction at the PIM device results in an error and a predetermined latency period expires from when the idempotent instruction is issued.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: May 23, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Nuwan Jayasena, Sudhanva Gurumurthi, Shaizeen Aga, Shrikanth Ganapathy
  • Patent number: 11645130
    Abstract: A resource manager (RM) instance is associated with each transaction processing system (TPS) member, of a TPS group. Each RM instance monitors performance of the associated TPS member. If a TPS member becomes unavailable for any reason (a failing TPS), the associated RM instance broadcasts status of the failing TPS to RMs associated “surviving” members of the group. RM instances associated with surviving members initiate a series of actions that reduce the resources used by the surviving TPS members. Consequently, the surviving TPS members are better able to process the additional workload imposed on them due to the unavailability of the failing TPS. Once the failing TPS is brought back online and made available again (or a replacement TPS is brought online), RM instances associated with the surviving members perform actions to undo the resource usage reduction tasks, and the TPS group returns to a nominal configuration.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: May 9, 2023
    Assignee: International Business Machines Corporation
    Inventors: Jack Chiu-Chiu Yuan, Jeffrey L. Maddix, Elvis B. Halcrombe, Chih-Fang Li
  • Patent number: 11630741
    Abstract: Disclosed herein are systems and method for backing up data in a load-balanced clustered environment. A clustered resource to be backed up is selected, wherein the clustered resource is stored on a common storage system and operated on by a cluster-aware application executing on at least a first node and a second node of a computing cluster. A load-balanced application may migrate the clustered resource from the first node with a high-load consumption to the second node with low-load consumption. A list of changes made by both nodes are received and merged. A backup agent then generates a consistent incremental backup using data retrieved from the common storage system according to the merged list of changes to the clustered resource.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: April 18, 2023
    Assignee: Acronis International GmbH
    Inventors: Anatoly Stupak, Dmitry Kogtev, Serguei Beloussov, Stanislav Protasov
  • Patent number: 11599419
    Abstract: A method for execution by a computing device of a storage network includes obtaining storage performance information for a set of storage units of the storage network, where data segments are dispersed storage error encoded into pluralities of sets of encoded data slices in accordance with error encoding parameters that include a pillar width number and a decode threshold number, which is a number of encoded data slices the set of encode data slices is required to reconstruct a data segment of data segments. The method further includes determining, based on the storage performance information and the error encoding parameters, a performance threshold number for a write request to store a set of encoded data slices of the pluralities of sets of encoded data slices in the set of storage units, where the performance threshold number is greater than the decode threshold number and less than the pillar width number.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: March 7, 2023
    Assignee: Pure Storage, Inc.
    Inventors: Greg R. Dhuse, Jason K. Resch, Andrew D. Baptist, Ilya Volvovski
  • Patent number: 11593214
    Abstract: The disclosure provides a reset device and a display device. The reset device comprises a processor, a reset circuit and a button. The reset circuit electrically connects to the processor and the button. When the button is not pressed, the processor acquires a first level signal from the reset circuit; when the button is pressed, if the processor cannot recognize the second level signal while acquiring the second level signal from the reset circuit, the display device is restarted; and during or after restart operation for the display device, if the reset circuit detects that the first level signal and the second level signal which are output by the reset circuit before and after the button is pressed are different, software fault recovery operation is performed on the display device.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: February 28, 2023
    Assignee: Hisense Visual Technology Co., Ltd.
    Inventors: Xiaolong Li, Juncai Yu, Yanjie Zheng
  • Patent number: 11561739
    Abstract: A persistent memory unit for a computer system where the memory unit can detect a catastrophic event and automatically backup volatile memory into non-volatile memory. The memory unit can operate with a limited number of power inputs and detect the loss of power and then initiate a backup after the volatile memory of the memory unit has entered a stable self-refresh mode. The memory unit uses an on-board power management interface controller capable of redistributing power from an input power line and generating different power levels for different components on the memory unit.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: January 24, 2023
    Assignee: SMART Modular Technologies, Inc.
    Inventor: Kelvin Alberto Marino
  • Patent number: 11558243
    Abstract: During operation, an electronic device may store, in memory, information associated with operation of the electronic device, such as during communication and processing of one or more packets or frames. Furthermore, an error-event monitor in the electronic device may, during a time interval, analyze at least a portion of the stored information to detect an occurrence of an error event in one or more types of error events in the electronic device. When the error event occurs during the time interval, the electronic device may perform a remedial action and may persist, in the memory, at least a second portion of the stored information associated with the error event. Otherwise, when the error event does not occur during the time interval, the electronic device may overwrite, in the memory, the stored information with additional information associated with operation of the electronic device during subsequent communicating and processing.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: January 17, 2023
    Assignee: ARRIS Enterprises LLC
    Inventors: Renjith Kumar Ponnappan, Sanjeev Nand Chhabria, Rubasri Pandian, Sophronia Alexander, Thamaraiselvan Gajendran
  • Patent number: 11544130
    Abstract: A watchdog circuit for monitoring a plurality of virtual machines provided by one core of a plurality of cores. The watchdog circuit may include a first memory portion, a second memory portion, and a control logic configured to count a number of pulses, to, when starting the watchdog circuit, store a global watchdog counter value in the first memory portion, and to store a local counter value for each virtual machine of the one or more virtual machines in the second memory portion, and, after a predefined number of pulses, to modify the global watchdog counter value and the local counter values, and, if the global watchdog counter value fulfills a predefined global watchdog reference criterion or any of the local watchdog counter values fulfills a predefined local watchdog reference criterion, to output an error signal.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: January 3, 2023
    Assignee: Infineon Technologies AG
    Inventors: Sai Kiran Bollu, Ananth Kamath