Abstract: Disclosed is a low cost contact and interconnect layer and method for fabricating the same. A contact via is opened within an insulating layer, exposing a circuit node (e.g., transistor active area within a semiconductor substrate). The via is filled with a chemical vapor deposited (CVD) titanium silicide layer, forming electrical contact with the circuit node. The silicide layer may simultaneously form the interconnect layer for one embodiment. In other embodiments, the interconnect layer may comprise a metal strap over the titanium silicide layer, or a metal layer over an etched-back titanium silicide plug in the contact via. For any of these embodiments, the contact via may be opened after the formation of interconnect trenches, the via extending from the bottom of a trench to the circuit node. CVD provides good step coverage of the via within the trench, despite the higher aspect ratio. The interconnect layer is deposited and etched back, such that the interconnect lines are defined by the trenches.

Abstract: A method for forming wiring layer of a semiconductor device for improving the step coverage and filling of the contact hole is disclosed. After forming an underlayer of the wiring layer on a semiconductor substrate, the surface of the underlayer is hydrogen-treated by exposing the underlayer to hydrogen plasma or hydrogen radicals to thereby H-terminate the surface portion of the underlayer. Thus, the characteristics of the underlying layer is improved. When depositing a metal such aluminum or aluminum alloy on the underlayer to thereby form a first conductive layer, large grains of the deposited metal are obtained. The step coverage of the deposited metal layer is enhanced and the mobility of the metal grains is increased. When sputtering the metal at a high temperature or when heat-treating the metal layer which has been formed at a low temperature, the filling of the metal into the contact hole is improved.

Abstract: Impurities are added to a conductor layer in a semiconductor process to prevent formation of void spaces and encourage complete filling of contacts. The impurities reduce the melting point and surface tension of a conductor layer, thereby improving filling characteristics during a reflow step. The impurities may be added at any time during the process, including during conductor deposition and/or reflow.