Abstract: A continuous ADC for generating a digital representation, corresponding to a given quantized voltage level, of an analog input signal and for updating the digital representation at times when the approximate amplitude of the analog signal changes from one quantized level to another. A preferred embodiment includes a set of serially connected output stages with each stage for generating a bit output signal included in the digital representation and an analog residual output signal having an amplitude equal to a linear combination of the amplitude of the input analog signal and the prior bit output signals.

Abstract: A method of digitizing an input analog current signal such as a demodulated servo position error signal in a disk file includes charging a capacitor with the input demodulated signal, and comparing the resulting capacitor voltage with a plurality of thresholds to produce a comparator output signal for each threshold exceeded by the capacitor voltage. The comparator output signals are sampled, and each sampling period a current corresponding to the thresholds exceeded is generated. The generated current is used to draw off charge from the capacitor until an equilibrium voltage is reached. By knowing the current generated to remove from the capacitor the voltage placed thereon by the input current signal, then the total charge applied to the capacitor can be determined. Further digital processing of the input signal value may be done without the use of a complicated digital to analog converter.

Abstract: A very high speed optical converter for converting digital signals from Gray code to binary code and vice versa. The converter implements an exclusive-OR function. The converter may be constructed with fiber optic technology, AlGaAs ridge waveguide technology, LiNbO technology and other technologies.

Abstract: A converter for digital radio applications, consisting of a parallel analogue to digital converter that provides a sampling at signal carrier frequency, or preferably at a harmonic of this frequency. Successive samples are stored in a memory and this is accessed at a lower rate to average numbers of samples. The ADC achieves greater resolution by virtue of this sampling. Filtering is provided by averaging action, but further filtering functions can be performed by an add-on filter. The converter receives modulated analogue signal from an input stage, for example the rf. or if. circuit of a radio receiver. In a modified version of the apparatus, several converters may be utilized in parallel to afford increased data colletion.

Abstract: The electromagnetic braking arrangement comprises an exciting winding which is supplied from a generator winding which on the one hand excites the generator winding and on the other hand induces a braking torque in a short-circuited winding moved with the generator winding. The excitation current of the exciting winding is controlled by a transistor of a current-regulating circuit which holds the excitation current and thus the braking torque at a level adjustable at a reference voltage source. The iron circuit of the exciting winding has residual magnetic properties which ensure an initial self-excitation. The components of the control circuit are supplied with operating voltage from the generator winding via a rectifier circuit. A resistor, which is directly connected to the rectifier circuit, controls the transistor in the conductive state even when the operating voltage is insufficient for proper operation of the control circuit.

Abstract: An arrangement of switches and resistors for switching current into the summing node of an integrator uses a pair of switches for each resistor. Each resistor is connected at one end to a reference voltage. The other end of the resistor is connected to a first switch, which is in turn connected to the summing node. A second switch is connected between ground and the junction of the resistor and the first switch. One or the other of the two switches will always be on. When the first switch is on and the second one is off a current will flow from the reference voltage, through the resistor and into the summing node. When the first switch is off and the second one is on essentially the same current will flow from the reference voltage, through the resistor and into ground. The current will be nearly the same, since the virtual ground of the integrator approximates actual ground.

Abstract: A method for performing oversampled analog-to-digital conversion of an input signal to generate a conversion result signal essentially free of systematic errors in accordance with the invention includes the steps of: performing oversampled analog-to-digital conversion of the input signal to generate a preliminary conversion result signal accompanied by systematic error, performing oversampled analog-to-digital conversion of a zero-valued signal to generate a correction signal essentially consisting of a corresponding systematic error, and differentially combining the correction signal and the preliminary conversion result signal to generate the conversion result essentially free of systematic errors. In a structural embodiment of the invention the systematic error in an oversampled analog-to-digital converter is suppressed by subtracting from the conversion response the response of a similar oversampled analog-to-digital converter to the reference voltage as its analog input signal.

Abstract: An overload detector for an analog-to-digital converter. A series of logic gates are connected to the output of an analog-to-digital converter for determining the presence of an upper limit and a lower limit of an overload condition. A signal indicative of such a condition is input to circuitry which extends the length of the signal so that it is visible or audible to a user. An algorithm for a computer causes a latch to be engaged when an overload condition occurs. The latch is coupled to a pulse stretching circuit which permits a visible or audible signal to be generated.

Abstract: Herein disclosed is an oversampling type A/D converter, wherein there are connected in multiple stages units interpolation type A/D conversion circuits each including: an analog integration circuit for integrating the difference between an analog input signal and a feedback signal; a voltage comparison circuit for adding the integrated signal and said difference to produce a digital signal on the basis of the added value; a digital integration circuit for integrating the digital signal coming from the voltage comparison circuit; a feedback load D/A conversion circuit for producing a feedback signal from the output of the digital integration circuit; and an addition circuit for adding the output and input of said digital integration circuit.

Abstract: Analog-to-digital converter is particularly for digital systems requiring a fast and accurate high resolution conversion of an analog input signal into a corresponding digital output code. A comparator compares the input signal against a ramp signal. A plurality of counters is responsive to the comparator for providing the output code. Each counter has a weight and counts subsequently to the counting of the counter having a higher weight. A digital-to-analog converter converts the output code from the counters into a reference signal prior to the counting of each counter. An integrator provides the ramp signal in reference to the reference signal and at a rate corresponding to the weight of the counter currently counting. A switch zeroes the integrator prior to the counting of each counter. An optional flash analog-to-digital converter estimates the input signal and determines an initial count of the counters.

Abstract: A dual successive approximation analog-to-digital converter, including circuitry for generating separate reference voltages for each analog-to-digital converter, is integrated onto a single semiconductor chip. A single successive approximation register including a 19 bit shift register and two 18 bit latches and associated gating circuitry operates to produce two sets of 18 successive approximation numbers, one supplied as successive digital inputs to a CDAC of one of the analog-to-digital converters and the other set of successive approximation numbers being applied as digital inputs to a CDAC of the other analog-to-digital converter. A CMOS comparator includes two high speed, low gain differential amplifier stages, the first including cascode MOSFETs to provide a high power supply rejection.

Abstract: In a cyclic averaging analog to digital converter, reference voltages having a plurality of levels, each of which is inputted to one of a plurality of comparators in a flash type analog to digital converter, are shifted cyclically by a small voltage, and the outputs of the flash type analog to digital converter are added for every shift cycle in order to obtain an output digital signal. The outputs of a voltage dividing circuit provide the reference voltages with N levels, the levels differing cyclically by a small voltage. The N reference voltages are divided into groups, each of which consists of M elements N/M, switches are provided each of which selects one of the reference voltages one after another for an associated group N/M reference voltages are thus selected by these switches and are supplied to the comparators.

Abstract: The same analog signal is inputted to an 8-bit AD converter and to a 4-bit AD converter to obtain an 8-bit digital data and a 4-bit digital data for the same sample value of the analog signal. Values of the 8-bit digital data and 4-bit digital data are compared with each other. The 8-bit digital data is outputted as a digital signal for the sample value of the analog signal when a difference between these values is not greater than one-half the quantity that corresponds to the least significant bit of the 4-bit digital data, and the 4-bit digital data is outputted as a digital signal for the sample value of the analog signal in other cases. There is realized AD conversion which operates apparently at high speeds maintaining high accuracy.

Abstract: An A/D converter circuit generates a precise digital signal which accurately corresponds to an analog input signal. The A/D converter comprises a converter element, having a first and second, input terminal for receiving control signals, and having an output terminal, and further having at least one analog input terminal. The analog input signal is coupled to the analog input terminal, for converting the analog input signal to an uncorrected digital signal. The uncorrected digital signal includes inaccuracies of the parameter differentials of the converter element. A memory unit, stores information defining the actual parameter values of the converter element. A processor, controls the conversion of the analog input signal to the precise digital signal, wherein the actual parameter values are applied to the uncorrected digital signal thereby removing the inaccuracies of the converter element to obtain the precise digital signal.

Abstract: A digital-to-analog converter which comprisesan input terminal (1) for receiving a digital input signal,an output terminal (2) for supplying the analog output signal,a current source circuit (3) having N current sources (I.sub.1 to I.sub.N) for generating N currents of substantially equal current intensity at N outputs (3.1 to 3N), anda combination circuit (4) having N inputs (4.1 to 4N) coupled to the N outputs of the current source circuit and an input (6) for receiving the digital input signal and an output (7).In order to convert a digital signal D which is presented to the input terminal (1) during a time interval (Ta), the time interval is sub-divided into at least two sub-intervals (T.sub.d1, T.sub.d2).

Abstract: An encoder device encodes angular position in the form of electrical signals in dependence on the position of a rotatable member in relation to a series of discrete fixed contacts disposed about the axis of rotation of a rotatable member. A series of discrete fixed contacts 2a, 2b, carried by a panel 1, form a first group of contacts of a flexible switch structure which also has a second group of contacts 9 carried by a flexible sheet 7 and arranged such that each contact of the second group is located opposite to, but spaced from, one of the series forming the first group of contacts. An intermediate sheet 8 is sandwiched between the panel 1 and flexible sheet 7 and is apertured at 10 in the region of the contact sets 2a, 2b and 9.

Abstract: In digital-to-analog converters with "rotating" current sources for converting an n-bit binary signal to an analog output signal, a single cyclic shift register is replaced by m cyclic shift register portions each having p=(2.sup.n -1)/m inputs, and the n-digit binary signal to be converted is changed into the thermometer code by means of a code converter. The middle output of the code converter and equal numbers of code converter outputs on both sides thereof are connected to one of the shift register portions. According to the same rule, the code converter outputs located further from the middle are connected to the other shift register portions. Thus, a clock signal serving as a shift signal for the shift register portions only needs to have a frequency which is p times that of the sampling signal with which an, e.g., analog, audio signal is digitized.

Abstract: An encoder for detecting the state of movement of a scale having a plurality of tracks consisting of arranged predetermined codes comprises first detecting device for reading the codes of the plurality of tracks and detecting data comprising a row of the codes, and second detecting device for detecting the state of movement of the codes of a particular track plurality of tracks to obtain more detailed data. The state of movement of the scale is detected on the basis of the signals from the first and second detecting devices.

Abstract: In a digital-to-analog conversion circuit, a level detector is used to determine when the digital signal is lower than a predetermined value. When a predetermined time has expired, after the level detection, an inversion detector detects an inversion in polarity of the digital signal. As a result, a control signal is produced to shift the digital signal input to the digital-to-analog (D/A) converter and to attenuate the output analog signal.

Abstract: There is provided a method of modulating a data bit series consisting of a first value (e.g. 1) and a second value (e.g., 0) whereby a transition as a state transition is caused so as to satisfy the following conditions of (a) to (d).(a) The transition at the boundary portion of the bit cell which is sandwiched by bits 0.(b) The transition at the central portion of the bit cell of bit 1.(c) Among an even number of the bits of 1 which are sandwiched by bits 0, the transition is inhibited at the central portion of each bit cell of the last two bits of 1 and the transition is caused at the boundary portion of these two bit cells of 1.(d) When at least one bit in a pattern which starts from the two bits of (01) appears at a location next to an even number of the bits of 1 subsequent to bit of 0, the transition is caused at the central portion of the bit cell of bit 0 between these two bits.