Patents Examined by Gary L. Laxton
  • Patent number: 10554145
    Abstract: An electrical power conversion apparatus includes a high-voltage bus bar, a low-voltage bus bar, and a relay bus bar which are integrated together in the form of a bus bar assembly. The high-voltage bus bar includes semiconductor-side high-voltage terminals and capacitor-side high-voltage terminals. The low-voltage bus bar includes semiconductor-side low-voltage terminals and capacitor-side low-voltage terminals. The relay bus bar includes a reactor-side relay terminal and a capacitor-side relay terminal 532. The capacitor-side high-voltage terminals, the capacitor-side low-voltage terminals, and the capacitor-side relay terminal are arranged in the form of a terminal array. The capacitor-side high-voltage terminals and the capacitor-side low-voltage terminals are arranged adjacent each other. The capacitor-side relay terminal is located at an end of an array of the capacitor-side high-voltage terminals and the capacitor-side low-voltage terminals.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: February 4, 2020
    Assignee: DENSO CORPORATION
    Inventors: Naoki Hirasawa, Ryota Tanabe, Taijiro Momose
  • Patent number: 10554124
    Abstract: A multi-level buck converter is provided with multiple control loops to regulate the output voltage in the presence of over-current conditions and in the vicinity of a 50% duty cycle.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: February 4, 2020
    Assignee: DIALOG SEMICONDUCTOR (UK) LIMITED
    Inventors: Aravind Mangudi, William McKillop, Mark Mercer, Muhammad Nabeel Rahman, Kevin Dowdy
  • Patent number: 10554140
    Abstract: An AC-DC converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided for reducing the cost, complexity and size of the converter while improving efficiency. Generally, the secondary side controller includes a zero-crossing detector block, a negative-sensing block, a peak-detector block and a line-feed-forward block integrated in an integrated circuit (IC), and coupled to a secondary side of the converter through a single SR-sense (SR_SNS) pin through which the IC is coupled to a drain of the SR. The single SR_SNS pin has a maximum input voltage less than a rectified AC input voltage input to a secondary side of the converter, and, in one embodiment, is coupled to the drain of the SR through a voltage divider circuit including circuit elements both internal and external to the IC along with a rectifier element in series with the internal resistor.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 4, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Arun Khamesra, Hariom Rai, Pulkit Shah
  • Patent number: 10554129
    Abstract: A buck converter includes a power switch having one end to which an input voltage is transferred, a synchronous switch connected between the other end of the power switch and the ground, an inductor having an end connected to the other end of the power switch, and a switch control circuit configured to calculate a zero voltage delay time based on at least an ON time of the power switch and a delay time. The delay time is determined based on the inductor and parasitic capacitors of the power switch and the synchronous switch.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: February 4, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: SangCheol Moon, Gwanbon Koo, Chenghao Jin, Bonggeun Chung
  • Patent number: 10554200
    Abstract: Peak detection methods, apparatus, and circuits are disclosed. An example peak detector includes a first peak-hold circuit having a first input terminal and a first output terminal, the first peak-hold circuit to determine a first peak of a rectified input voltage at the first input terminal during a first time interval, and to track a second peak of the rectified input voltage during a second time interval, the second time interval distinct from the first time interval, and a second peak-hold circuit having a second input terminal and a second output terminal, the second peak-hold circuit to determine, during the second time interval, a greater of the first peak and the second peak, the first output terminal coupled to the second input terminal, the greater of the first peak and the second peak output at the second output terminal.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: February 4, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Maxim James Franke, Michael Ryan Hanschke, Antonio Amoroso, Rosario Stracquadaini
  • Patent number: 10547237
    Abstract: A power conversion system includes a feedback controller circuit connected between the output of a boost converter and a duty cycle control input of the boost converter. The feedback controller circuit comprises: a first summing node which generates an error signal indicative of a difference between a voltage of the output of the boost converter and a reference voltage, a compensator circuit receiving the error signal and applying a gain to the error signal to generate an amplified error signal, and a scaling circuit for scaling the amplified error signal to generate a scaled signal, which is applied to a duty cycle control input of the boost converter to alter the duty cycle and/or pulse frequency of the boost converter. The feedback controller circuit provides a frequency-dependent impedance transformation looking into the boost converter from the source such that instability due to line impedance is reduced.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: January 28, 2020
    Assignee: MKS Instruments, Inc.
    Inventor: Pericles N. Bakalos
  • Patent number: 10546682
    Abstract: A reactor comprises a first coil, a second coil and a core. Each of the first coil and the second coil is embedded in the core. The core has an outer core part, an inner core part, an upper core part, a lower core part and a middle core part. The upper core part is positioned above an upper end of a cross-section of the first coil in an up-down direction. The lower core part is positioned below a lower end of a cross-section of a second coil in the up-down direction. The core is made of a first member and a second member. The second member has a relative permeability which is greater than a relative permeability of the first member. Each of the upper core part and the lower core part is made of the second member.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: January 28, 2020
    Assignee: TOKIN CORPORATION
    Inventors: Yuki Abe, Takashi Yanbe, Masahiro Kondo, Takuya Endou, Keisuke Akaki
  • Patent number: 10547304
    Abstract: A semiconductor integrated circuit for driving a control terminal of a switching device includes: a driver circuit that alternately applies a positive voltage supplied from a positive voltage source and a negative voltage supplied from a negative voltage source to the control terminal in order to switch the switching device ON and OFF; and a negative voltage clamp diode that is integrated into a semiconductor chip on which the driver circuit is formed, an anode thereof being connected to the negative voltage source and a cathode thereof being connected to the control terminal.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: January 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Patent number: 10541620
    Abstract: A two-wire load control device (such as, a dimmer switch) for controlling the amount of power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) includes a thyristor coupled between the source and the load, a gate coupling circuit coupled between a first main load terminal and the gate of the thyristor, and a control circuit coupled to a control input of the gate coupling circuit. The control circuit generates a drive voltage for causing the gate coupling circuit to conduct a gate current to thus render the thyristor conductive at a firing time during a half cycle of the AC power source, and to allow the gate coupling circuit to conduct the gate current at any time from the firing time through approximately the remainder of the half cycle, where the gate coupling circuit conducts approximately no net average current to render and maintain the thyristor conductive.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: January 21, 2020
    Assignee: Lutron Technology Company LLC
    Inventor: Robert C. Newman, Jr.
  • Patent number: 10541623
    Abstract: A circuit topology and switching scheme for a circuit that includes an input voltage divider configured to provide a divided voltage that may be approximately half of a supply voltage. The circuit also includes a switching circuit with a first half-bridge that includes a first switching node and a second half-bridge that includes a second switching node. One or more switches are configured to connect the divided voltage to the first switching node and the second switching node.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: January 21, 2020
    Assignee: Infineon Technologies AG
    Inventor: Vratislav Michal
  • Patent number: 10541647
    Abstract: Transconductance (gm)-cell based circuitry is well suited for low power, low voltage complementary metal oxide silicon (CMOS) design in deep sub micro technology. This circuitry includes a gm cell as the basic building block. As such, it is desirable to have the transconductance of the gm cell to be constant against temperature and process corners. The present disclosure describes various gm-cell based circuitry having a controllable transconductance. Preferably, the controllable transconductance can be selectively controlled to be equal to the inverse of the value of an on-chip resistor. For example, the gm-cell based circuitry can sense the transconductance of an internal replica unit and can use negative feedback circuitry to cause this transconductance to be approximately equal a value of an on-chip resistor. However, in some situations, a value of this on-chip resistor is not accurately controlled.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: January 21, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Howard Chi, Seema B. Anand
  • Patent number: 10534388
    Abstract: A driver circuit includes a temperature sensor generating a first voltage representative of current operating temperature. An amplifier compares the first voltage to a second voltage representative of an upper threshold operating temperature, and generates a control signal based thereupon. A variable current source generates a load current from the control signal. The amplifier generates the control signal to cause the variable current source to generate the load current as having a magnitude equal to an upper threshold when the first voltage is less than the second voltage. The amplifier generates the control signal to cause the variable current source to generate the load current as having a magnitude that is decreasing until the first and second voltages are equal, and then generates the control signal to cause the variable current source to maintain the load current magnitude at a level at which the first and second voltages are equal.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: January 14, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventor: Santo Ilardo
  • Patent number: 10536088
    Abstract: In some embodiments, upon detecting a fault condition, switching in a switched mode power supply is disabled only after a current switching cycle of the switched mode power supply is completed.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: January 14, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ming Ping Mao, Tong Bao, Yaw Hann Thian, Weifu Yu
  • Patent number: 10536083
    Abstract: Systems, methods, and apparatus for a circuit with power factor correction (PFC) are disclosed. In one or more embodiments, the disclosed method comprises providing, by a single-stage power converter, a delay in phase between a peak current command and a rectified input voltage such that a phase of a transformer current intentionally lags behind a phase of the rectified input voltage to maintain a power factor (PF) level and a total harmonic distortion (THD) level for the single-stage power converter. In one or more analog embodiments, a resistor and a capacitor are implemented into a conventional single-stage power converter to provide the delay in phase between the peak current command and the rectified input voltage. In one or more digital embodiments, a controller within a conventional single-stage power converter exclusively provides the delay in phase between the peak current command and the rectified input voltage.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: January 14, 2020
    Assignee: Dialog Semiconductor Inc.
    Inventor: Xiaolin Gao
  • Patent number: 10536079
    Abstract: A method for discontinuous conduction mode operation of a multi-phase DC-to-DC converter includes (a) forward biasing a first inductor being magnetically coupled to a second inductor, (b) reverse biasing the first inductor after forward biasing the first inductor, (c) while reverse biasing the first inductor and before magnitude of current through the first inductor falls to zero, forward biasing the second inductor.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: January 14, 2020
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Xin Zhou, Justin Michael Burkhart, Michael Warren Baker, Brett A. Miwa
  • Patent number: 10534384
    Abstract: A current mode switching regulator circuit and operating method includes a variable duty cycle power switch controller, a voltage feedback loop that provides a feedback signal based on the output voltage, a current feedback loop that provides a current sense signal based on the output current, and an offset circuit having an external signal input and coupled to the current feedback loop. The power switch controller controls the switching regulator circuit to generate an output voltage and an output current. The offset circuit is configured to provide an offset output control signal, independently of the voltage feedback loop, to control the power switch controller so as to vary a duty cycle of the power switch controller based on the current sense signal and an external offset signal applied to the external signal input.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: January 14, 2020
    Assignee: Linear Technology Corporation
    Inventors: Gregory Manlove, James McKenzie, Robert Chiacchia, Yi Ding Gu, Jian Li
  • Patent number: 10536068
    Abstract: A systematic procedure for the synthesis of hybrid feedforward control architectures for pulse-width modulated (PWM) switching converters is provided. In this hybrid feedforward control architecture selected converter variables are sensed and utilized in a particular way based on the converter open-loop characteristics to determine the duty-cycle needed to achieve a control objective. Compared to standard feedback control techniques, advantages can include simpler controller implementation, more convenient sensing, and improved static and dynamic regulation. An example systematic procedure for developing hybrid feedforward controllers is illustrated by first considering a previously known example of hybrid feedforward control: hybrid feedforward control of a boost power factor correction (PFC) rectifier operating in discontinuous conduction mode (DCM).
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: January 14, 2020
    Assignee: The Regents of the University of Colorado, a body corporate
    Inventors: Usama Anwar, Khurram K. Afridi, Dragan Maksimovic
  • Patent number: 10536072
    Abstract: A circuit includes a transformer configured with a primary winding and a secondary winding that are driven from a voltage supplied by a thermoelectric generator (TEG). The circuit includes a bipolar startup stage (BSS) coupled to the transformer to generate an intermediate voltage. The BSS includes a first transistor device coupled in series with the primary winding of the transformer to form an oscillator circuit with an inductance of the secondary winding when the voltage supplied by the TEG is positive. A second transistor device coupled to the secondary winding of the transformer enables the oscillator circuit to oscillate when the voltage supplied by the TEG is negative. After startup, a flyback converter stage can be enabled from the intermediate voltage to generate a boosted regulated output voltage.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: January 14, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Nachiket Venkappayya Desai, Yogesh Kumar Ramadass
  • Patent number: 10530268
    Abstract: A load control device for controlling the power delivered from an AC power source to an electrical load includes a thyristor, a gate coupling circuit for conducting a gate current through a gate of the thyristor, and a control circuit for controlling the gate coupling circuit to conduct the gate current through a first current path to render the thyristor conductive at a firing time during a half cycle. The gate coupling circuit is able to conduct the gate current through the first current path again after the firing time, but the gate current is not able to be conducted through the gate from a transition time before the end of the half-cycle until approximately the end of the half-cycle. The load current is able to be conducted through a second current path to the electrical load after the transition time until approximately the end of the half-cycle.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: January 7, 2020
    Assignee: Lutron Technology Company LLC
    Inventors: Robert C Newman, Jr., Daniel F. Carmen, Christopher J. Salvestrini, Matthew V. Harte
  • Patent number: 10530274
    Abstract: A method for operating a transformerless inverter includes operating first and second half-bridges of the inverter using a unipolar clocking method as a first clocking method, determining a value of a grid-frequency stray current at the DC terminals of the inverter during the unipolar clocking method, and when a limit value is exceeded by the stray current value, operating the first and second half-bridges of the inverter using a stray-current-reducing clocking method as a second clocking method in which the first half-bridge provides an AC voltage at the first AC output, wherein an amplitude of the AC voltage is less than 50% of the amplitude of a voltage amplitude of the grid, and the second half-bridge provides a difference voltage between the grid voltage and the voltage provided by the first half-bridge at the first AC output.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: January 7, 2020
    Assignee: SMA Solar Technology AG
    Inventors: Burkard Mueller, Klaus Rigbers, Wilfried Vogt