Abstract: An analog-to-digital converter quantizer and bidirectional counter using superconducting quantum interference devices (SQUD's) as the principal elements. A double-junction non-latching SQUID is used as a quantizer to produce unipolar output pulses on two different output lines, indicative of positive and negative increments of change in an analog signal current. The unipolar pulses are then counted in a bidirectional counter that employs double-junction non-latching SQUID's as counter stages and as logic gates for the propagation of carry and borrow signals from stage to stage.

Abstract: A digital-to-analog converter for converting a digital signal having a word length n into an analog signal comprises a series arrangement of at least two integrating circuits (1,2) and a control unit (18) for supplying a first and a second control signal (S1, S2) to the first and the second integrating circuit. The integrating circuits are adapted to perform an integration step under the influence of the first and the second control signal. The control unit is adapted to generate, in this order, the first control signal M1 times, the second control signal M2 times, the first control signal M3 times and the second control signal M4 times. For converting arbitrary digital signals M2+M4 is equal to a constant (k). Due to this measure an offset voltage which is independent of the value of the n-bit digital signal to be converted is produced at the output (8) of the converter. For converting n-bit digital signal the constant k is preferably taken to be equal to 2.sup.p in which p.ltoreq.n.

Abstract: An information-transmission system including an encoder for converting n-bit information words (D7, . . . , D0) into transmitted m-bit code words (C10, . . . , C0), and a decoder which reconverts the received code words (C'10, . . . , C'0) into information words (D*7, . . . , D*0) corresponding to the original information words. For a first group the encoder converts a first portion (D7, . . . , D3) into a first portion of a code word, such portion comprising q bits (C10, . . . , C5) thereof; and converts a second portion (D2, . . . , D0) of the information word into a second portion of the code word, such portion comprising s bits (C4, . . . , C0) thereof. For a second group the encoder converts a first portion (D7, . . . , D3) into a second portion comprising q bits (C'5, . . . , C'0) of a code word, and converts a second portion (D2, . . . , D0) of the information word into a first portion comprising s-bits of (C'10, . . . , C'6) such code word.

Abstract: The invention is applicable to delta modulation. A method of codifying the bit-stream for more efficient storage and transmission is disclosed. The number of pulses from the a-to-d converter is counted, per batch of B clock beats. The count, or tally value T of the batch, may be issued as an N-bit group, e.g. a 4-bit nibble. The order and spacing of the pulses within the batch is ignored. When the signal is rebuilt, a batch of B clock beats are counted out, T of which are pulses. One value which the nibble can take is reserved and used to indicate a period of silence, by replacing a whole frame of silent nibbles. Both a fixed frame length and a variable frame length are disclosed. For greater sensitivity, the extreme tally values may be utilized to signal a change in the gain or response of the system. A median tally value may be used to cancel the gain change.