Abstract: An example computer-implemented method for synchronously programming multiple memory modules includes sending one or more instructions to each of the memory modules to perform a first data operation associated with a computer software update. In response to determining that each of the memory modules have received the first instructions to perform the first data operation, time is spent waiting for the first data operation to be completed at each of the memory modules. One or more instructions are also sent to each of the memory modules to perform a second data operation associated with the computer software update. In response to determining that each of the memory modules have received the second instructions to perform the second data operation, time is spent waiting for the second data operation to be completed at each of the memory modules. Furthermore, the data is validated across the memory modules.

Abstract: A memory system includes a nonvolatile memory including a plurality of blocks and a controller configured to write data to a plurality of write destination blocks allocated from the plurality of blocks. The controller is configured to in response to receiving a read command from a host, increment a first counter value corresponding to a first block having a block address allocated to a logical address of read target data specified by the received read command. The controller is configured to read the read target data from the first block or a buffer depending on whether the read target data is readable from the first block, and decrement the first counter value corresponding to the first block. The controller is configured to prohibit processing for transitioning a state of a block associated with an uncompleted read command to a state reusable as a new write destination block.

Abstract: Presented herein are systems and methods for configuring devices with write operations. One or more processors can identify a first sequence of write operations to configure a device. Each write operation in the first sequence of write operations can identify a set of a value and an address to which to write the value. The one or more processors can determine one or more distances between a set of the value and the address of a write operation and at least one other set of the value and the address of one or more other write operations in the first sequence of write operations. The one or more processors can generate a second sequence of write operations based at least on the one or more distances. The one or more processors can cause the device to be configured using the second sequence of write operations.

Abstract: There is provided a recording apparatus that records data to a memory card, comprising: a control unit configured to repeatedly transmit a data recording instruction that includes information designating recording target data and a recording destination to the memory card which manages a memory for data recording in the memory card as a plurality of recording areas and which can execute data recording with a guaranteed minimum recording speed in units of recording areas, wherein when transmitting a first data recording instruction that designates a start portion of a first recording area as a recording destination, the control unit requests the memory card to execute data recording with the guaranteed minimum recording speed with respect to the first recording area by including a speed guarantee request in the first data recording instruction.

Abstract: In examples there is a computing device comprising a processor, the processor having a memory management unit. The computing device also has a memory that stores instructions that, when executed by the processor, cause the memory management unit to receive a memory access instruction comprising a virtual memory address; translate the virtual memory address to a physical memory address of the memory, and obtain permission information associated with the physical memory address. Responsive to the permission information indicating that metadata is permitted to be associated with the physical memory address, a check is made of a metadata summary table stored in the physical memory to check whether metadata is compatible with the physical memory address. Responsive to the check being unsuccessful, a trap is sent to system software of the computing device in order to trigger dynamic allocation of physical memory for storing metadata associated with the physical memory address.

Abstract: A data processing method includes: detecting, when writing first block data into a local cache and a local storage, a first block processing space of a storage buffer pool; writing, when a number of block data to be stored does not reach a buffer block processing threshold, the first block data into the storage buffer pool based on N block data to be stored; detecting a second block processing space of a storage processing pool; and determining, when a number of block data to be fed back does not reach a feedback block processing threshold, block data to be merged for overlap detection with the block data to be fed back in the storage buffer pool based on the number of the block data to be fed back and the feedback block processing threshold, and writing the data retained after overlap detection to a distributed database.

Abstract: Disclosed is an operation method of a storage device, which includes a plurality of data processing engines includes setting a first region among a plurality of regions of a host memory buffer allocated from an external host with a first data processing policy and setting a second region among the plurality of regions with a second data processing policy, performing an encoding operation on data to be stored in the first region, based on a first data processing engine corresponding to the first data processing policy, performing an encoding operation on data to be stored in the second region, based on a second data processing engine corresponding to the second data processing policy, and changing the first data processing policy of the first region to a third data processing policy based on a changed characteristic of the first region.

Abstract: A cloud-based data protection service is disclosed. In an embodiment, the data protection service may support backup of data sets from one or more sites associated with one or more organizations. In an embodiment, deduplication of backup data across multiple sites of an organization and/or multiple sites associated with different organizations may be supported. In an embodiment, backup data may be post-processed in the cloud to insert fingerprints corresponding to data blocks that did not change since a previous backup was performed, to scan the backup for security threats such as viruses, other malware, personally identifiable information, etc. In an embodiment, restore may be supported from the cloud, where restore blocks may be larger than backup data blocks. In another embodiment, restore may be based on blocks that have changed since the most recent backup (or a user-selected backup).

Abstract: According to one embodiment, a storage device comprises a nonvolatile memory, and a controller configured to perform a first data write operation in a first mode, and to perform a second data write operation in a second mode. Data of a first number of bits is written per memory cell in the first mode. Data of a second number of bits is written per memory cell in the second mode. The second number is larger than the first number. The controller reserves one or more free blocks as write destination block candidates of the first data write operation, perform the first data write operation for one of the write destination block candidates, and perform a garbage collection.

Abstract: A system includes a memory device containing multiple dies that each have multiple pages, and a processing device, operatively coupled with the memory device, to perform various operations including scanning a group of pages residing on a die and determining a value of one data state metric and a corresponding value of another state metric. The operations can also include recording a set of values of the first metric and a corresponding set of values of the second metric, as well as calculating the value of the second metric corresponding to a predetermined value of the first metric associated with a failure condition of the die. Additionally, the operations can include identifying a particular criterion that is satisfied by the calculated value, assigning, to the die, a rating corresponding to the identified criterion, and performing scans on the die at a frequency determined by the assigned rating.

Abstract: Systems and methods for address mapping for a memory system are described. A system address that includes a first set of bits may be received. The first set of bits may be partitioned into at least a second set of bits and a third set of bits. A fourth set of bits may be determined based on the second set of bits. A memory address may be determined by using the third set of bits and the fourth set of bits.

Abstract: Methods, systems, and devices for metadata implementation for memory devices are described. A memory device may read metadata, transfer the metadata to a buffer, and read information. For example, the memory device may receive a read command from a host device to read information. The memory device may execute a first internal read command to read the metadata associated with the information. Upon reading the metadata, the memory device may store the metadata in the buffer (e.g., one or more latches). Upon determining that a duration has elapsed, the memory device may execute a second internal read command to read the information associated with the metadata. The memory device transmits the information and the metadata to the host device. In some other cases, the memory device may write information, store metadata in a buffer, and write the metadata (e.g., a different order than for read operations).

Abstract: A processor to generate accumulated data comprising, for an operation cycle: performing an operation on a first bit range of a set of first input data to generate a set of operation data, which is accumulated with stored data within a first storage device. A lowest n bits of the accumulated data are accumulated with first further stored data within a first bit range of a second storage device, and are bit-shifted from the first storage device. Further accumulated data is generated, comprising, for an operation cycle: performing the operation on a second bit range of the set of first input data to generate a further set of operation data, which is accumulated with the stored data within the first storage device. A lowest m bits of the further accumulated data is accumulated with second further stored data within a second bit range of the second storage device.

Abstract: A computer-implemented method for allocating memory bandwidth of multiple CPU cores in a server includes: receiving an access request to a last level cache (LLC) shared by the multiple CPU cores in the server, the access request being sent from a core with a private cache holding copies of frequently accessed data from a memory; determining whether the access request is an LLC hit or an LLC miss; and controlling a memory bandwidth controller based on the determination. The memory bandwidth controller performs a memory bandwidth throttling to control a request rate between the private cache and the last level cache. The LLC hit of the access request causes the memory bandwidth throttling initiated by the memory bandwidth controller to be disabled and the LLC miss of the access request causes the memory bandwidth throttling initiated by the memory bandwidth controller to be enabled.

Abstract: Techniques are disclosed relating to multi-block fetches for cache misses. In some embodiments, cache tag circuitry maintains a tag value that is shared by multiple cache blocks. In response to a miss, the cache may initiate a fetch request to a next level cache or memory. Aggregation circuitry may aggregate multiple fetch requests for cache blocks that share the tag value and fetch circuitry may initiate a single multi-block fetch operation to the next level cache or memory that returns cache blocks for the aggregated multiple fetch requests. In various embodiments, disclosed techniques may improve performance (e.g., by reducing fetch bus transactions), reduce power consumption, or both, relative to traditional techniques.

Abstract: In an example, a method includes storing code for a first central processing unit (CPU) executing a first application in a first region of a memory, and storing code for a second CPU executing a second application in a second region of the memory. The method includes storing shared code for the first CPU and the second CPU in a third region of the memory. The method includes storing read-write data for the first CPU in a fourth region of the memory and storing read-write data for the second CPU in a fifth region of the memory. The method includes translating a first address from a first unique address space for the first CPU to a shared address space in the third region, and translating a second address from a second unique address space for the second CPU to the shared address space in the third region.

Abstract: One example method includes receiving, by a first computing entity from a second computing entity, a request for data, providing, by the first computing entity, a compliance API (Application Program Interface) to the second computing entity, receiving, by the first computing entity from the second computing entity, location information and/or data compliance information, by way of the compliance API, consulting, by the first computing entity, a mapping, and determining, based on information in the mapping and the location information and/or data compliance information, whether or not the data is permitted to be transmitted by the first computing entity to the second computing entity, and either transmitting the data to the second computing entity, or not transmitting the data to the second computing entity, based on data tags, the information in the mapping and the location information and/or data compliance information.

Abstract: A method of contention-free lookup including mapping a key of a cache lookup operation to determine an expected location of object data, walking a collision chain by determining whether a cache header signature matches a collision chain signature, when the cache header signature does not match, again walking the collision chain, when the cache header signature matches, determining whether a key in the cache header signature matches the key of the cache lookup operation, when the key does not match, reading a cache entry corresponding to the cache lookup operation, and repopulating the cache entry, when the key matches, acquiring an entry lock, and determining whether the key still matches after acquiring the entry lock, when the key still matches finding the object data in the expected location, and when the key no longer matches, releasing the entry lock, and again walking the collision chain.

Abstract: The present application discloses a memory chip, an operating method thereof, and a judging method. The operating method of the memory chip includes steps of: constructing the memory chip including at least two nonvolatile register groups, wherein each of the nonvolatile register groups includes a flag register and at least one register, and stored data of each of flag registers is configured to indicate at least one storage state of the at least one register in a same one of the nonvolatile register groups. obtaining the stored data of at least one of the flag registers; judging whether the stored data of the at least one of the flag registers is random code; and erasing all of the nonvolatile registers if the stored data of the at least one of the flag registers is the random code.

Abstract: A memory module may include J memory chips configured to input/output data in response to each of a plurality of translated address signals; and an address remapping circuit configured to generate a plurality of preliminary translated address signals by adding first correction values to a target address signal provided from an exterior of the memory module, and to generate the plurality of translated address signals by shifting all bits of each of the plurality of preliminary translated address signals so that K bits included in a bit string of each of the plurality of preliminary translated address signals are moved to other positions of each bit string.