Abstract: A sub-word line driver circuit includes a substrate, a plurality of gate lines, at least one gate tab, and a variable-thickness gate dielectric. The substrate includes an isolation area and an active area. The gate lines are arranged in a first direction and extend in a second direction perpendicular to the first direction. The gate tab extends in the first direction to cover the isolation area, in which the gate lines and the gate tab form at least one gate region on the substrate. The variable-thickness gate dielectric includes a thick gate dielectric region disposed over a first portion of the active area, and a thin gate dielectric region disposed over a second portion of the active area.

Abstract: Disclosed is a semiconductor device including internal power supply generating circuits for generating internal power supplies and data terminals via which data signals are output or input/output. The internal power supply monitor terminals are in common use with the data terminals. The semiconductor device also includes selection circuits for selecting, by a test control signal, whether or not output voltages of the internal power supply generating circuits are to be output to the data terminals.

Abstract: A method and a circuit are for regulating the source terminal voltage of a non-volatile memory cell during the cell programming and/or reading phases. The method includes a phase of locally regulating the voltage value and includes comparing the source current of the cell array with a reference current. A fraction of the source current is converted to a voltage and compared with a voltage generated from a memory cell acting as a reference and being programmed to the distribution with the highest current levels. The comparison may be used for controlling a current generator to inject, into the source terminal, the current necessary to keep the predetermined voltage thereof at a constant value.

Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.