Abstract: A storage cell includes a bit storage member capable of storing a data bit. The bit storage member includes a true data output, having a true data value corresponding to the data bit, and a complement data output, having a complement data value corresponding to a logical complement of the true data value. A first controllable gate is electronically coupled to the true data output and is responsive to a first read enable signal so that the true data value is passed through the first controllable gate when the first read enable signal is asserted. A second controllable gate is electronically coupled to the complement data output and is responsive to a second read enable signal so that the complement data value is passed through the second controllable gate when the second read enable signal is asserted.