Patents Examined by Geoffrey R St Leger
  • Patent number: 11977475
    Abstract: A system to support validation and debugging of compiled low-level instructions for a machine learning (ML) network model on an ML-specific hardware. A compiler identifies well-defined boundaries in the ML network model based on primitives used to generate low-level instructions for the hardware. The ML network model is partitioned into units/layers/sub-graphs based on the plurality of well-defined boundaries. The compiler then generates an internal representation for each of the units wherein the internal representation is mapped to components in the hardware. Each of the units is compiled into a first set to be executed on the ML-specific hardware and a second set to be executed on a second computing device. The output results from executing the two sets of low-level instructions are compared to validate the first set of low-level instructions. If the outputs do not match fully, the first set of low-level instructions is debugged and recompiled.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: May 7, 2024
    Assignee: Marvell Asia Pte Ltd
    Inventors: Chien-Chun Chou, Senad Durakovic, Ulf Hanebutte, Harri Hakkarainen, Yao Chou, Veena Karthikeyan
  • Patent number: 11977613
    Abstract: A system including at least one processor programmed to translate a policy into policy code, wherein: the policy is provided in a policy language; the policy code is in a programming language that is different from the policy language; and the policy includes a statement that maps an entity name to one or more metadata symbols to be associated with an entity in a target system against which the policy is to be enforced.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: May 7, 2024
    Assignees: Dover Microsystems, Inc., The Charles Stark Draper Laboratory, Inc.
    Inventors: Eli Boling, Steven Milburn, Gregory T. Sullivan, Andrew Sutherland, Christopher J. Casinghino
  • Patent number: 11972237
    Abstract: Improved compilers recognize interception declarations in source code, and emit code that replaces invocations of specified artifacts with invocations of specified interceptors instead. Source generators proactively modify program behavior in arbitrary desired ways without introducing hidden security violations and without requiring edits by the program's developers. Interception declarations are visible in source code and development tools. In some cases, different invocations of a particular method at respective locations are intercepted by different replacement methods. Replacement methods have identical signatures, or are otherwise compatible. Some interceptors specify optional parameters. Method calls, field accesses, and property calls may be intercepted. Work to modify program behavior is moved in the program lifecycle from runtime to compile time, thus improving runtime performance and eliminating JIT compilation security risks.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: April 30, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jared Parsons, David Fowler, Jan Kotas, Stephen Harris Toub, Richard Steele Gibson, Andrew Spenser Gocke, Julien David Couvreur, Christopher Sienkiewicz
  • Patent number: 11972250
    Abstract: Examples of performing an out-of-band firmware update of a server computing device are described. In an example, a first disk image is mounted onto a server computing device. The first disk image comprises a bootable firmware and is mounted in response to a mount command received through an out-of-band communication service. In another example, a second disk image is also mounted onto the server computing device. The second disk image is also mounted in response to another mount command received through the out-of-band communication service and is to provide a read-writable container, when mounted. Thereafter, a booting process of the server computing device may be initiated based on mounted first image to update the firmware of the server computing device. Information related to the update of the firmware is store in the read-writable container.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: April 30, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Aneesh George, Mekhla Garg, Sreejith Kumar Kurikal Veedu
  • Patent number: 11966727
    Abstract: The disclosure invention provides a method for executing a program compiled for a source architecture on a machine having a different target architecture, a non-transitory computer readable medium configured to store instructions for performing such a method, and a system for performing such a method.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: April 23, 2024
    Assignee: LzLabs GmbH
    Inventors: Jan Jaeger, Thomas D. Grieve
  • Patent number: 11954477
    Abstract: The present disclosure relates to an information processing device, an information processing method, and a program capable of suppressing labor and cost for generating a unique identifier. According to the present disclosure, provided is an information processing device provided with software in which first identification information having uniqueness is registered, and an application that obtains the first identification information from the software, converts the first identification information into second identification information having uniqueness for communication, and registers the second identification information in the software. With this configuration, it is possible to suppress labor and cost for generating a unique identifier.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: April 9, 2024
    Assignee: FELICA NETWORKS, INC.
    Inventor: Yasuo Takeuchi
  • Patent number: 11941374
    Abstract: The present invention generally relates to system, method and graphical user interface for executing one or more tasks in dynamic data driven enterprise application. The invention includes creation of rules on a rule creation interface by one or more syntax from a rule creation syntax data library. The invention provides machine learning models driven rule engine for executing the tasks.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: March 26, 2024
    Assignee: NB Ventures, Inc.
    Inventors: Subhash Makhija, Saratendu Sethi, Huzaifa Matawala, Manish Sharma, Shivendra Singh Malik, Srishti Kush
  • Patent number: 11941391
    Abstract: A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. The uCode hot-upgrade method applies a uCode patch to a firmware storage device (e.g., BIOS SPI flash) through an out-of-band controller (e.g., baseboard management controller (BMC)). In conjunction with receiving a uCode patch, a uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for persistent storage and live-patch without touching the tenant operating system environment.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Mohan J. Kumar, Sarathy Jayakumar, Chuan Song, Ruixia Li, Xiaojin Yuan, Haiyue Wang, Chong Han
  • Patent number: 11934816
    Abstract: Generation of an executable file derived from a parent executable file having ranges of physical addresses referencing a binary code of at least one core feature (CR), a binary code of a set of native features (F), bytecodes of a set of java features (Pkg), by selecting at least one native feature from the set of native features to be removed, defining the range of physical addresses where the binary code of the selected native feature is stored, selecting at least one java feature from the set of java features to be relocated, and relocating the bytecodes of said at least one selected java feature in the defined range of physical addresses.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: March 19, 2024
    Assignee: THALES DIS FRANCE SAS
    Inventors: Damien Bertonnier, Nicolas Regnault, Valérie Martin
  • Patent number: 11934821
    Abstract: A device management system includes an automatic updater that automatically generates an automatic F/W update task in accordance with an automatic F/W update plan which is a setting for automatically generating the automatic F/W update task as a task for updating firmware of an image forming apparatus. The automatic F/W update plan includes specifying of firmware for update and a mode in which the update is fully executed on all electronic apparatuses of a target of the software update. The automatic updater automatically generates the automatic F/W update task in accordance with the automatic F/W update plan at a specific timing in a repeat manner.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: March 19, 2024
    Assignee: KYOCERA DOCUMENT SOLUTIONS INC.
    Inventors: Chika Tsuji, Hisakazu Nishiyama, Jumpei Takagi, Atsushi Matsumoto
  • Patent number: 11930093
    Abstract: Aspects of managing inventory for data transport connections within a virtualized computing environment are described. A virtualized management system managing a cluster of host devices obtains a data transport capacity parameter and an aggregate memory consumption value from respective host devices. The virtualized management system further identifies an update status associated with each of the host devices. In response to receiving a data transport connection request, the virtualized management system selects a host from the cluster of hosts to satisfy the data transport connection request based at least in part on the upgrade status, data transport capacity parameter and aggregate memory consumption value.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: March 12, 2024
    Assignee: VMware, Inc.
    Inventors: Varun S. Lingaraju, Lei Lu, Maarten Wiggers, Pradeep Ramachandra
  • Patent number: 11921862
    Abstract: Systems and methods for rules-based automated penetration testing and regression to certify release candidates against known patterns that inject vulnerabilities are disclosed.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: March 5, 2024
    Assignee: JPMORGAN CHASE BANK , N.A.
    Inventor: Ambika Prasad Pathak
  • Patent number: 11922138
    Abstract: A method for providing a federated, multi-product data mesh via automated code generation is disclosed. The method includes receiving, via an application programming interface, a data model, the data model including model artifacts that define data governance for a data product; automatically generating source code for software components based on the data model, the software components corresponding to data mesh components for the data product; integrating data product customizations into the software components, the data product customizations including business logics and testing configurations; initiating an automated continuous integration and continuous delivery pipeline to generate a service that corresponds to the data product based on the integrated software components; and deploying the generated service in a namespace that corresponds to the data product.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: March 5, 2024
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Deepak Ghosh, Srikanth Jagrothu, Ian Mark Miller
  • Patent number: 11907109
    Abstract: An apparatus comprises a processing device configured to obtain testing logs generated by executing test cases on information technology assets of an information technology infrastructure, to parse the testing logs to generate a set of log event templates for testing actions performed during execution of the test cases on the information technology assets of the information technology infrastructure, to generate vector representations of the test cases utilizing the generated set of log event templates, and to perform, utilizing one or more machine learning-based hierarchical clustering algorithms that take as input the generated vector representations of the test cases, hierarchical clustering of the plurality of test cases. The processing device is also configured to generate, based at least in part on the hierarchical clustering results, testing plans for a given information technology asset of the information technology infrastructure.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: February 20, 2024
    Assignee: Dell Products L.P.
    Inventors: Nan Wang, Chi Chen, Jing Ye, Yang Wu
  • Patent number: 11900075
    Abstract: In some implementations, a device may generate, based at least in part on a first set of inputs, a serverless software development environment associated with a set of cloud resources. The device may generate, based at least in part on a first machine learning model, a technology stack recommendation having a set of associated tools for performing a software development task. The device may instantiate the selected technology stack in the serverless software development environment and generate a set of applications based at least in part on executing the set of tools. The device may deploy the set of applications in one or more serverless application environments. The device may use machine learning to observe deployed applications, detect hidden anomalies, and perform root-cause analysis, thereby providing a lean and sustainable serverless environment.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: February 13, 2024
    Assignee: Accenture Global Solutions Limited
    Inventors: Rajendra Prasad Tanniru, Aditi Kulkarni, Koushik M. Vijayaraghavan, Vijeth Srinivas Hegde, Ravindra Kabbinale, Sreenath Kothavoor, Amrutha Pervody Bhat, Meghana B Srinath, Ravi Kiran Singh, Dilip Krishnan, Naveen Raj K P, Sumanth Channegowda, Vinay Chamarthi, Lakshmi Srinivasan, Santhosh Mv
  • Patent number: 11893370
    Abstract: According to one aspect, a method for compiling by a compilation tool a source code into a computer-executable code comprises receiving the source code as input of the compilation tool, translating the source code into an object code comprising machine instructions executable by a processor, then introducing, between machine instructions of the object code, additional instructions selected from illegal instructions and no-operation instructions so as to obtain the executable code, then delivering the executable code as output of the compilation tool.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: February 6, 2024
    Assignee: STMicroelectronics (Grand Ouest) SAS
    Inventors: Michel Jaouen, Stephane Le Roy, Moise Gergaud
  • Patent number: 11886842
    Abstract: A development assistance device includes: multiple conversion units each converting either an inputted signal value or inputted meta information into either a signal value or meta information, and outputting either the signal value after conversion or the meta information after conversion as output information; a pipeline unit causing, on the basis of pipeline information showing a relationship of mutual connections between the multiple conversion units, the multiple conversion units to sequentially perform the corresponding converting processes; an inference unit making an inference by using the output information outputted by a final conversion unit which the pipeline unit causes, on the basis of the pipeline information, to finally perform the converting process, out of the multiple conversion units; and an image generation unit generating image information for visualizing the connection relationship shown by the pipeline information, and a relationship of a connection between the final conversion unit and
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: January 30, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takashi Matsumoto, Genta Yoshimura
  • Patent number: 11886332
    Abstract: In a dynamic memory allocator, a method of allocating memory to a process, the method comprising executing on a processor the steps of: creating one or more arenas within the memory, each arena comprising one or more memory blocks and each arena having an n-byte aligned arena address; upon receiving a memory request from the process, returning a pointer to the process, the pointer having as its value an address of a memory block selected from one of the arenas; upon determining that the memory block is no longer needed by the process, retrieving the address of said memory block from the pointer and releasing the memory block; and, upon a new arena being created, shifting forward the n-byte aligned address of said new arena according to a stored variable such that each memory block of said new arena is also shifted by the stored variable, the stored variable having n bytes and the stored variable having a random value.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: January 30, 2024
    Assignees: UNIVERSITAT POLITECNICA DE VALENCIA, CYBER INTELLIGENCE S.L.
    Inventors: Hector Marco Gisbert, Jose Ismael Ripoll Ripoll
  • Patent number: 11880695
    Abstract: This application provides a plug-in implementation system and method. The system includes a plug-in module and a terminal software module. When the terminal software module does not include a service implementation of a first plug-in interface, the plug-in module may load a default implementation of the first plug-in interface to invoke the first plug-in interface. In this way, a plug-in may be extended to extend a service function of a terminal. In addition, when the plug-in interface is inconsistent with a plug-in function, the default implementation of the plug-in interface is implemented by using the plug-in module, so that an open-source software module can run normally, to ensure normal running of an electronic device as much as possible. Therefore, the open-source software module no longer depends on the terminal software module, and the terminal software module can be decoupled from the open-source software module.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: January 23, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zhenchao Lin, Chao Ding, Linlin Tu, Jinfei Wang, Xiaoxuan Chen, Weisai Ning, Zhongling Chen, Lei Liu, Qinhua Jiang
  • Patent number: 11868731
    Abstract: According to an aspect of an embodiment, operations include receiving a set of NL descriptors and a corresponding set of PL codes. The operations further include determining a first vector associated with each NL descriptor and a second vector associated with each PL code, using language models. The operations further include determining a number of a set of semantic code classes to cluster the set of PL codes into the set of semantic code classes, based on the number, the first vector, and the second vector. The operations further include training a multi-class classifier model to predict a semantic code class, from the set of semantic code classes, corresponding to an input NL descriptor. The operations further include selecting an intra-class predictor model based on the predicted semantic code class. The operations further include training the intra-class predictor model to predict a PL code corresponding to the input NL descriptor.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: January 9, 2024
    Assignee: FUJITSU LIMITED
    Inventors: Mehdi Bahrami, Wei-Peng Chen