Abstract: A vertical bipolar transistor has a J-FET incorporated in an epitaxial layer. The pinch-off voltage of the J-FET is less than the collector-emitter breakdown voltage of a bipolar transistor without the J-FET.

Abstract: A novel fuse structure. An optimal position of laser spot is defined above a substrate. A first conductive layer is formed on part of the substrate. A dielectric layer is formed on the substrate and the first conductive layer. A second conductive layer comprising the position of laser spot is formed on part of the dielectric layer. A third conductive layer is formed on the part of the dielectric layer placed above the first conductive layer, wherein the third conductive layer is insulated from the first and second conductive layers. At least one conductive plug penetrates the dielectric layer, to electrically connect the first conductive layer and the second conductive layer. Thus, the third conductive layer serves as a floating layer to prevent the first conductive layer from being damaged in the laser blow process.

Abstract: A semiconductor device includes an array of electrical fuses having a structure which permits tight fuse pitches while enabling electrical fusing at voltages of about 10 volts or less. The fuses are useful to replace defective components of the device and/or to permit custom wiring. The semiconductor device includes a substrate with a tight pitch array of fuses including a plurality of fuse links of selective cross sectional area in closely adjacent arrangement, each connected at one end to an individual connector terminal of larger cross sectional area than that of the fuse link, and at another end to a common connector terminal of larger cross sectional area than that of the individual connector terminals. The common connector terminal is typically held at a less positive potential than one of the individual connector terminals during the time a fuse link thereat is to be opened such that electron flow is in a direction from the common connector terminal to the fuse link.

Abstract: A CMOS device includes a first MOS transistor of a surface channel type and a second MOS transistor of a buried channel type on a common substrate wherein a doped layer is provided underneath a first channel layer of the first MOS transistor and a second channel layer of the second MOS transistor, such that the first channel layer is provided at a level closer to a principal surface of the substrate as compared with source and drain regions of the first and second MOS transistors.