Patents Examined by George Giroux
  • Patent number: 10416998
    Abstract: A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventor: Shih Shigjong Kuo
  • Patent number: 10394559
    Abstract: A computer-implemented method includes determining, by a stream-based index accelerator predictor of a processor, a predicted stream length between an instruction address and a taken branch ending an instruction stream. A first-level branch predictor of a hierarchical asynchronous lookahead branch predictor of the processor is searched for a branch prediction in one or more entries in a search range bounded by the instruction address and the predicted stream length. A search of a second-level branch predictor of the hierarchical asynchronous lookahead branch predictor is triggered based on failing to locate the branch prediction in the search range.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz
  • Patent number: 10353683
    Abstract: A system for dynamically generating a timeout value based on a customer runtime environment for use with a manufacturer update package. More specifically, the system for dynamically generating a timeout value decomposes calculation of a timeout value based upon the major steps contained within the update service and dynamically calculates the timeout value based upon processor load. In certain embodiments the system uses a heuristic algorithm to perform the calculation.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: July 16, 2019
    Assignee: Dell Products L.P.
    Inventors: Jianwen Yin, Yong Cao, Xianghong Qian
  • Patent number: 10346199
    Abstract: An exception handling system is described herein that provides one or more distinguished classes of software exceptions that are handled differently than other exceptions. The system treats a distinguished exception as a “hard to catch” exception that is not passed to the catch block of program code unless a developer performs extra steps to acknowledge the distinguished nature of the exception and confirm that the program code is prepared to properly handle the exception. Exceptions that fall into this class are typically those that represent conditions from which normal exception handling practices cannot successfully recover, namely exceptions that corrupt application state. Accordingly, the system prevents the developer from catching these classes of exceptions by default unless the developer explicitly requests to have these exceptions delivered to the program code. Thus, the exception handling system encourages correct programming practices by preventing developer error by default.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: July 9, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Andrew J. Pardoe, Michael M. Magruder, Kumar Gaurav Khanna, Diana Milirud, Gaye Oncul Kok
  • Patent number: 10331191
    Abstract: Technologies are generally described herein for supporting program and data annotation for hardware customization and energy optimization. A code block to be annotated may be examined and a hardware customization may be determined to support a specified quality of service level for executing the code block with reduced energy expenditure Annotations may be determined as associated with the determined hardware customization. An annotation may be provided to indicate using the hardware customization while executing the code block. Examining the code block may include one or more of performing a symbolic analysis, performing an empirical observation of an execution of the code block, performing a statistical analysis, or any combination thereof. A data block to be annotated may also be examined. One or more additional annotations to be associated with the data block may be determined.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 25, 2019
    Assignee: Empire Technology Development, LLC
    Inventor: Miodrag Potkonjak
  • Patent number: 10318284
    Abstract: A method, computer program product, and system of managing computing tasks includes storing at least one build information element within at least one attribute of a configuration management tool A computing task is generated from within the configuration management tool based upon, at least in part, the at least one build information element. The computing task is initiated from within the configuration management tool. The computing task is deployed on a computing device.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brandt William Onorato, Stephen Donald Seifert, Anthony T. Lee, Ray Kemmer Green
  • Patent number: 10303478
    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 10296344
    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: May 21, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 10296349
    Abstract: Data processing circuitry comprises allocation circuitry to allocate one or more source and destination processor registers, of a set of processor registers each defined by a respective register index, to a processor instruction for use in execution of that processor instruction and to associate, with the processor instruction, information to indicate the register index of the allocated source and destination processor registers; the avocation circuitry being selectively operable to allocate, to a processor instruction, a group of destination processor registers having a subset of their register indices in common and to associate, with the processor instruction, information to indicate the register index of one processor register of the group and identifying information to identify one or more bits of the register index which differ between the processor registers in the allocated group of processor registers.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: May 21, 2019
    Assignee: ARM Limited
    Inventors: Vladimir Vasekin, Antony John Penton, Chiloda Ashan Senarath Pathirane, Andrew James Antony Lees
  • Patent number: 10296341
    Abstract: A processor and system for latest producer tracking In one embodiment, the processor includes an operand renamer circuit that includes a register rename map, a producer tracking circuit that includes a producer tracking map, and a results buffer allocater circuit that includes a results buffer free list. Control logic modifies in-register status values stored in the register rename map based on producer tracking status values stored in the producer tracking map. The producer tracking status values stored in the producer tracking map are modified based on buffer identification values output by the results buffer allocater circuit.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: May 21, 2019
    Assignee: ARM Finance Overseas Limited
    Inventors: Kjeld Svendsen, Xing Yu Jiang
  • Patent number: 10275242
    Abstract: An apparatus and method are described for real time instruction tracing. For example, a method according to one embodiment comprises: recording user specified address ranges for which tracing is required; monitoring a next linear instruction pointer (NLIP) values and/or branch linear instruction pointer (BLIP) values to determine if address range has been entered; when the range is entered, compressing the NLIP and/or BLIP values and constructing fixed length packets containing the tracing data; and transferring the fixed length packets to a memory execution cluster.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Huy V. Nguyen, Jason W. Brandt, Jonathan J. Tyler
  • Patent number: 10275249
    Abstract: Embodiments include a method comprising: executing a loop during a first encounter of the loop; tracking a first number of times the loop is iterated while the loop is executed during the first encounter; executing the loop during a second encounter of the loop; tracking a second number of times the loop is iterated while the loop is executed during the second encounter; and in response to the first number being equal to the second number, predicting a behavior of the loop during a third encounter of the loop.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: April 30, 2019
    Assignee: Marvell International Ltd.
    Inventors: Daniel J. Richins, Joseph Delgross
  • Patent number: 10261792
    Abstract: In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Michael W. Chynoweth, Peggy J. Irelan, Matthew C. Merten, Seung-Woo Kim, Laura A. Knauth, Stanislav Bratanov
  • Patent number: 10229089
    Abstract: A method and apparatus for efficiently processing data in various formats in a single instruction multiple data (“SIMD”) architecture is presented. Specifically, a method to unpack a fixed-width bit values in a bit stream to a fixed width byte stream in a SIMD architecture is presented. A method to unpack variable-length byte packed values in a byte stream in a SIMD architecture is presented. A method to decompress a run length encoded compressed bit-vector in a SIMD architecture is presented. A method to return the offset of each bit set to one in a bit-vector in a SIMD architecture is presented. A method to fetch bits from a bit-vector at specified offsets relative to a base in a SIMD architecture is presented. A method to compare values stored in two SIMD registers is presented.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 12, 2019
    Assignee: Oracle International Corporation
    Inventors: Amit Ganesh, Shasank K. Chavan, Vineet Marwah, Jesse Kamp, Anindya C. Patthak, Michael J. Gleeson, Allison L. Holloway, Roger Macnicol
  • Patent number: 10223118
    Abstract: Providing references to previously decoded instructions of recently-provided instructions to be executed by a processor is disclosed herein. In one aspect, a low resource micro-operation controller is provided. Responsive to an instruction pipeline receiving an instruction address, the low resource micro-operation controller is configured to determine if the received instruction address corresponds to an instruction address in short history table. Short history table includes instruction addresses of recently-provided instructions having micro-ops in a post-decode queue. If the received instruction address corresponds to an instruction address in short history table, the low resource micro-operation controller is configured to provide reference (e.g., pointer) to the fetch stage that corresponds to an entry in the post-decode queue in which the micro-ops corresponding to the instruction address are stored.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: March 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Vignyan Reddy Kothinti Naresh, Shivam Priyadarshi, Raguram Damodaran
  • Patent number: 10223123
    Abstract: In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: March 5, 2019
    Assignee: Apple Inc.
    Inventors: Conrado Blasco, Brett S. Feero, David Williamson, Ian D. Kountanis, Shih-Chieh Wen
  • Patent number: 10203954
    Abstract: Instructions and logic provide conversions between a mask register and a general purpose register or memory. Some embodiments, responsive to an instruction specifying: a destination operand, a mask length corresponding to a number of mask data fields, and a source operand; values are read from data fields in the source operand, corresponding to the specified mask length, and stored to corresponding data fields in the destination operand specified by the instruction, wherein one of the source or the destination operands is a mask register. Values indicative of masked vector elements may be stored to any data fields in the destination operand other than the number of data fields corresponding to the specified mask length. For some embodiments, the other one of the source or the destination operands may be a general purpose register or a memory location.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Jesus Corbal, Robert Valentine, Bret L. Toll, Mark J. Charney
  • Patent number: 10185569
    Abstract: Interrupt handling on a multiprocessor computer executing multiple computational operations in parallel is provided by establishing a total ordering of the multiple computational operations and defining an architectural state at the time of the interrupt as if the computational operations executed in the total ordering.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: January 22, 2019
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Gagan Gupta, Gurindar S. Sohi
  • Patent number: 10175985
    Abstract: A processor core includes an instruction-sequencing unit (ISU). The ISU includes a general register file (GRF) composed of multiple hardware general purpose registers (GPRs), an exception register (XER), and a reservation station (RS). The execution unit(s) load an address of data in a data GPR, and load a first portion of the data in a first data GPR and a second portion of the data in a second data GPR in the GRF, where loading the portions of the data generate intermediate data condition codes that are loaded in the XER. The execution unit(s) generate a cumulative data condition code, which is loaded into a history buffer within the ISU. The intermediate data condition codes are loaded into a reservation station (RS) within the ISU. Upon flushing the GRF and the XER, the ISU repopulates the GRF from a history buffer and the XER from the RS.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sundeep Chadha, Michael J. Genden, Dung Q. Nguyen
  • Patent number: 10152324
    Abstract: Embodiments of methods and computer program products disclosed herein relate to processor architecture. One such method includes the processor obtaining an instruction. The instruction specifies an operation, and also specifies one of the registers as a source register and one of the registers as a destination register. The method also includes the processor obtaining an endian mode and determining that the instruction is an element-ordering-sensitive instruction. Based on the determination that the instruction is an element-ordering-sensitive instruction, the processor executes the instruction by performing the operation on the elements of the source register in accordance with the endian mode and writing a result of the operation to the destination register.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: December 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Brett Olsson