Abstract: An apparatus and method for obtaining a string representation of objects in a displayed hierarchical structure are provided. With the apparatus and method, a list having separators may be converted into a path equivalent for a specified hierarchical structure. In order to convert the separated list into a textual representation for an object in a hierarchical structure, an input string having separators is received and the cell renderer for a hierarchical structure is identified. Comparisons between portions of the separated list are compared to string representations for objects in the hierarchical structure in order to identify matches and ultimately, a path in the hierarchical structure corresponding to the separated list. The string representations for the objects are obtained by identifying the cell renderer component that is used to paint the object on a display.

Abstract: An image rescue system includes an application program for communication with a mass storage device, the application program being in communication with an operating system layer for accessing the mass storage device to read and write information, in accordance with an embodiment of the present invention. The image rescue system further includes a device driver in direct communication with the application program, and in communication with the operating system layer and the mass storage device, the mass storage device allowing the application program to search information in the mass storage device considered damaged by the operating system layer, the damaged information being inaccessible to the operating system layer.

Abstract: An approach to selecting either an actual stepping revision ID value or a compatible revision ID value to be readable by a processor through a revision ID register.

Abstract: In one aspect of the invention is a method to synchronize accesses by multiple threads to shared resources. The method entails a first thread entering a processing queue to contend for a lock on a shared resource. If a second thread exists, where the second thread is currently executing code, then the first thread may execute the critical section of code if the second thread is not currently executing the critical section; or if the second thread is currently executing the critical section of code, then the first thread may continue to contend for ownership of the shared resource until the second thread relinquishes ownership of the shared resource, or until a yield count expires.

Abstract: A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: A method and apparatus are provided for implementing a variable-partitioned queue for simultaneous multithreaded processors. A value is stored in a partition register. A queue structure is divided between a plurality of threads responsive to the stored value in the partition register. When a changed value is received for storing in the partition register, the queue structure is divided between the plurality of threads responsive to the changed value.

Abstract: A Distributed Object System includes an Event Collection Mechanism (14) which receives information on the creation, deletion and actuation of objects within the system. The Event Collection Mechanism passes on the collected events to an Event Dispatch Mechanism (16) with which user applications may register. The Event Dispatch Mechanism forwards details of events to the User Applications, according to the criteria selected by the user. A method is provided for linking all reported events back to the object which was ultimately responsible for their creation.

Abstract: A method schedules execution contexts in a computer system based on memory interactions. The computer system includes a processor and a hierarchical memory arranged in a plurality of levels. Memory transactions are randomly sampled for a plurality of contexts. The contexts can be threads, processes, or hardware contexts. Resource interactions of the plurality of contexts is estimated, and particular contexts are chosen to be scheduled based on the estimated resource interactions.

Abstract: A software-implemented method for validating the correctness of parallel computer programs, written in various programming languages, with respect to these programs' corresponding sequential computer programs. Validation detects errors that could cause parallel computer programs to behave incorrectly or to produce incorrect results, and is accomplished by transforming these parallel computer programs under the control of a general purpose computer and sequentially executing the resulting transformed programs. The validation method is system-independent and is portable across various computer architectures and platforms since validation is accomplished via program transformation; thus, the method does not depend on the features of a particular hardware architecture or configuration, operating system, compiler, linker, or thread environment. The input to the validation method is a parallel computer program.

Abstract: A method and apparatus for improving the process of determining whether two computer system memory references are exactly dependent. While loop unrolling creates a large number of memory reference pairs which must be analyzed during the data dependence analysis phase of compiler optimization, this invention reduces the computer resources required for this analysis. When two memory references are exactly dependent, the present invention quickly determines the distance between them by an elegant method which uses easily accessible values. Therefore, if two memory references are exactly dependent, and if the distance is an integral greater than zero then the compiler optimizer may re-use the same data in computer memory and thus reduce the need to execute computer register instructions. Alternately, if the two memory references are independent they become candidates for pipeline scheduling. This further reduces the use of computer resources.

Abstract: According to a first aspect of the present invention, a method for linking bytecodes of an uninterrupted block of bytecodes in the formation of a data flow graph comprises the steps of scanning the uninterrupted block of bytecodes in a forward manner to identify the start of each of the bytecodes, scanning in a backward manner bytecodewise each of the bytecodes in the uninterrupted block of bytecodes, and generating a link in the data flow graph that links each of the bytecodes to all other of the bytecodes used by the each of the bytecodes.

Abstract: In a computer system and a processor which has the capability to do multithreaded processor, the computer system and processor use idle register/storage functional units within the processor core to transfer the state of a thread out of the processor to memory or from memory to the processor core. The register/storage functional units are interrogated dynamically so that this transfer occurs only when the register/storage functional units are idle and not being used for normal instructions. Thus, a state may be transferred in whole if there are many cycles when the register/storage functional unit is idle or it may be transferred in part if there an insufficient number of no-op instructions for the entire state. A context switch unit in the processor then has appropriate registers and logic control to keep track of the state of the thread that is being “idly” transferred and then transfer the remaining registers when a register/storage functional is available or “idle.

Abstract: A computer program product simulates shared code threads with Windows NT fibers. Computer code is included for reusing shared code threads which complete.

Abstract: The present invention discloses a method, computer program product, and system for dynamically and programmatically modifying the semantics and/or logic of class files as they are being loaded for execution. The present invention permits a user to write a control file specifying in a programmatic manner the changes to be applied to class files and the conditions for carrying out the changes. As the class files are loaded, they are analyzed for the desired conditions and if the conditions are found, the control file is applied to them to effect the appropriate changes according to the user's control file.

Abstract: An enhanced unwind facility is more extensible, much faster, and uses smaller tables than presently known schemes. In broad terms, the unwind facility trades bytes that are used for addresses and region lengths in known schemes for a stream of bit fields parallel to the instruction stream. This arrangement allows an unwind library to compute a current regions' attributes by indexing instead of by a binary search. This arrangement also leads to an extensible design that does not require significant effort on an occurrence-by-occurrence basis in both the linker and the unwind library when additional services are required, e.g. register use areas for the debugging of optimized code.

Abstract: In a microprocessor embodiment (26), the microprocessor is operable to multi-task a plurality of programs, wherein the plurality of programs include a virtual program (38, 40) operable in a virtual mode and a monitor program (36) in a protected mode. The microprocessor includes an interrupt handling circuit (30) for executing an interrupt handler in response to a hardware interrupt request signal (HIM.cndot.INTR). The microprocessor further includes an interrupt flag bit (IF) set in a like manner in both the virtual mode and the protected mode. The interrupt flag bit is set in a first state to inhibit receipt of the hardware interrupt request signal by the interrupt handling circuit, and the interrupt flag bit is set in a second state to enable receipt of the hardware interrupt request signal by the interrupt handling circuit. The microprocessor further includes a virtual mode control signal (VM.cndot.

Abstract: Tile for use in forming a toy roadway, each tile having a roadway pattern formed on it and each tile having means for interlocking with similar adjacent tiles to form a complete system.