Abstract: The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is delimited by a peripheral edge. An n-doped trough is then produced in the semiconductor substrate by means of ion implantation using an energy that is sufficient for ensuring that a p-doped inner area remains on the surface of the semiconductor substrate. The edge area of the n-doped trough extends as far as the surface of the semiconductor substrate. The other n-doped and/or p-doped areas that make up the structure of the transistor or logic gate are then inserted into the p-doped inner area of the semiconductor substrate. The inventive method is advantageous in that it no longer comprises expensive epitaxy and insulation processes. In an n-doped semiconductor substrate, all of the implanted ions are replaced by the complementary species; i.e.

Abstract: A field effect transistor includes a substrate having a doping of a first conductivity type, a drain area in the substrate having a doping of a second conductivity type oppposite the first conductivity type, a source area in the substrate being laterally spaced from the drain area and having a doping of the second conductivity type, and a channel area in the substrate that is arranged between the source area and the drain area. In a portion of the substrate bordering the drain area, an area having a doping of the second conductivity type, which is connected to the drain area, is arranged such that in the portion alternating regions having the first conductivity type and having the second conductivity type are arranged.

Abstract: A contact plug is formed in a semiconductor device having a silicon substrate having a gate electrode, a junction area and an insulating interlayer. A contact hole is formed to expose the junction area. A plasma process is carried out with respect to a resultant substrate, thereby removing natural oxides created on an exposed surface of the junction area. A first silicon layer is deposited on the contact hole and on the insulating interlayer. A heat-treatment process is carried out with respect to the first silicon layer so as to grow the amorphous silicon into the epitaxial silicon. A second silicon layer is deposited on the first silicon layer.

Abstract: An aspect of the present invention provides a method of manufacturing a semiconductor device, including, forming an insulating film on a silicide layer formed at the surface of a silicon semiconductor substrate, etching the insulating film to form a contact hole in which the silicide layer is exposed, forming a metal nitride film on the bottom and side wall of the contact hole, carrying out a first heating process at 600° C. or lower on the substrate, carrying out, during the first heating process, a second heating process for 10 msec or shorter with light whose main wavelength is shorter than a light absorbing end of silicon, forming a contact conductor in the contact hole after the second heating process, and forming, on the insulating film, wiring that is electrically connected to the substrate through the contact conductor.

Abstract: An automatic wiring method for a semiconductor package includes: a provisional wiring step for sequentially specifying a plurality of lines of the terminals from the innermost periphery to the outermost periphery of bonding pads, connecting the bonding pads to predetermined vias present on the specified line of the terminal with line segments, and provisionally determining a wiring route for each line of the terminal such that the line segment passes through between the vias in each line of the terminal at equal intervals; and a wiring formation step for forming the wiring based on a design rule such that the wiring pattern passes through between the lines of the terminals with uniform intervals between wires based on the provisionally wired wiring routes.

Abstract: A resistor element has a ceramic body with a first outer electrode and a second outer electrode formed on its mutually opposite externally facing end surfaces and a plurality of mutually oppositely facing pairs of inner electrodes inside the ceramic body. Each of these pairs has a first inner electrode extending horizontally from the first outer electrode and a second inner electrode extending horizontally from the second outer electrode towards the first outer electrode and having a front end opposite and separated from the first inner electrode by a gap of a specified width, these plurality of pairs forming layers in a vertical direction. The gap of at least one of these plurality of pairs of inner electrodes is horizontally displaced from but overlapping with the gaps between the other pairs of inner electrodes. For producing such a resistor element, the distance of displacement is set according to a given target resistance value intended to be had by the resistor element.

Abstract: A low-resistance contact for use in integrated circuits is formed by creating a titanium silicide layer on a semiconductor body and treating the titanium silicide layer with active free nitrogen to form a surface comprised of titanium nitride. This titanium nitride surface is then overlaid with an additional deposition of titanium nitride. Finally, a layer of conductive metal, such as tungsten, is formed over the second titanium nitride layer by chemical vapor deposition. This process eliminates the need for a titanium-metal deposition step and the defects associated with potential reactions between tungsten hexafluoride gas and titanium metal.

Abstract: A method of making an EEPROM cell structure which includes two floating gate transistors separated by a select gate transistor with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor. The floating gates of the two transistors are formed from a first polysilicon layer, the control gates of the two transistors are formed from a second polysilicon layer, and the select gate is formed from a third doped polysilicon layer. The channel length of the select gate transistor is fully self-aligned to the floating gate transistors. A word line is formed over the control gates and forms the select gate. The word line runs generally perpendicular to bit lines which contact the drain regions of the two floating gate transistors. Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure.